Magnetic storage device
a magnetic storage and magnetic technology, applied in the field of magnetic storage devices, can solve the problems of increasing power consumption, large area, and increasing area
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first embodiment
[0072]As shown in FIG. 1, a magneto-resistance random access memory (MRAM) cell 10 in which a resistance value changes in accordance with storage information is constituted by connecting a magnetic change type resistance element 11 referred to as a magnetic tunneling junction (MTJ) and a selection transistor 12 for cell selection in series. One end of the MTJ 11 (on a side opposite to the transistor 12) is connected to a bit line BL as a data transfer line. A gate terminal of the transistor 12 is connected to a word line WL for the cell selection, a drain end thereof is connected to the MTJ 11, and a source end thereof is connected to the ground. It is to be noted that, although not shown, the MRAM cells 10 are two-dimensionally arranged in a row direction and a column direction. Furthermore, the cells of the same row are connected to the same bit lines BL, and the cells of the same column are connected to the same word lines WL.
[0073]As shown in FIG. 2, a reading signal line RL for...
second embodiment
[0098]The reading circuit 30 for use in the first embodiment might be influenced by the fluctuation of a manufacturing process. In particular, when the fluctuation of the judgment voltage of the inverter 34 is generated, an MRAM process margin is largely influenced.
[0099]The process margin is critical for relieving the influence on the process fluctuation of the MRAM cell 10. A relation between the process fluctuation of the inverter 34 and the process margin will hereinafter be described with reference to FIGS. 8 and 9.
[0100]The inverter 34 is a 1-bit A / D converter which receives a voltage Vi to be held at a time when the hold switch 31 is turned off and which judges whether this voltage is not less than Vdd / 2 or not more than Vdd / 2, to determine an output. The judgment voltage of the inverter 34 is determined in accordance with the balance of the characteristics of pMOS and nMOS transistors constituting this circuit. The input / output characteristics shown by a solid line in FIG. 8...
third embodiment
[0116]A third embodiment of the present invention will be described with reference to FIG. 13.
[0117]On the same chip, a memory cell array portion 100 is arranged adjacent to a dummy cell array portion 200. In the memory cell array portion 100, a plurality of bit lines BL are arranged in a row direction. In the dummy cell array portion 200, one reference bit line BL′ is arranged along the row direction. A plurality of word lines WL are arranged to straddle the memory cell array portion 100 and the dummy cell array portion 200 in a column direction.
[0118]In the memory cell array portion 100, MRAM cells 101 are arranged in intersecting portions between the bit lines BL and the word lines WL, respectively. Each of the MRAM cells 101 is constituted by connecting a magnetic change type resistance element and a selection transistor in series as determined in the first embodiment. One end of the MRAM cell 101 is connected to the bit line BL, and a gate of the selection transistor is connect...
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