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Two step optical planarizing layer etch

Inactive Publication Date: 2009-10-01
GLOBALFOUNDRIES US INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0004]A method is provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxid

Problems solved by technology

Immersion lithography's resolution enhancement is driven by the utilization of a higher numerical aperture lens (N.A.) which, however, results in a degradation of a depth of focus process window.
These challenges include the difficulty in maintaining CD retention thru the OPL layer and subsequent over-etch owing to isotropic characteristics during over-etch.
Failure to remove the Si infused portions of the mask during the oxide etch will dictate the use of an aggressive or non-selective ASH chemistry which will subsequently lead to an attack of the exposed nitride protecting the active areas which increases the likelihood of premature exposure of the underlying NiSi to the ASH chemistry.

Method used

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  • Two step optical planarizing layer etch
  • Two step optical planarizing layer etch
  • Two step optical planarizing layer etch

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Embodiment Construction

[0013]The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.

[0014]Referring to FIG. 1, a flow diagram 100 of a portion of the fabrication process of a semiconductor device in accordance with a preferred embodiment depicts a fabrication etch process methodology utilizing a tri-layer mask stack for patterning semiconductor device structures, the tri-layer mask stack particularly suitable for formation of semiconductor device structures having reduced critical dimensions, such as critical dimensions equal to or less than forty-five nanometers (45 nm). At such small critical dimensions, conventional lithography cannot be used to pattern the mask. Typically, advanced lithography techniques such as immersi...

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Abstract

Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Description

FIELD OF THE INVENTION[0001]The present invention generally relates to semiconductor fabrication etch process methodology, and more particularly relates to a two step Optical Planarizing Layer (OPL) etch process methodology.BACKGROUND OF THE INVENTION[0002]The transition to 45 nm semiconductor fabrication technology has seen the adoption of immersion lithography for critical levels. Only immersion lithography is capable of providing the resolution to resolve the minimum pitch features at such critical levels. Immersion lithography's resolution enhancement is driven by the utilization of a higher numerical aperture lens (N.A.) which, however, results in a degradation of a depth of focus process window. This depth of focus process window can be recovered by tuning the mask stack to minimize reflectivity. Typically, a tri-layer mask stack consisting of a layer of photoresist, a silicon containing anti-reflective coating (SiARC), and an optical planarizing under-layer (OPL) is utilized ...

Claims

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Application Information

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IPC IPC(8): H01L21/308
CPCH01L21/31144H01L21/0271
Inventor GEISS, ERIKPRINDLE, CHRISTOPHERBEYER, SVEN
Owner GLOBALFOUNDRIES US INC