Two step optical planarizing layer etch
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[0013]The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
[0014]Referring to FIG. 1, a flow diagram 100 of a portion of the fabrication process of a semiconductor device in accordance with a preferred embodiment depicts a fabrication etch process methodology utilizing a tri-layer mask stack for patterning semiconductor device structures, the tri-layer mask stack particularly suitable for formation of semiconductor device structures having reduced critical dimensions, such as critical dimensions equal to or less than forty-five nanometers (45 nm). At such small critical dimensions, conventional lithography cannot be used to pattern the mask. Typically, advanced lithography techniques such as immersi...
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