High temperature bd development for memory applications

Abstract

A method and apparatus for depositing organosilicate dielectric layers having good adhesion properties and low dielectric constant. Embodiments are described in which layers are deposited at low temperature and at high temperature. The low temperature layers are generally post-treated, whereas the high temperature layers need no post treating. Adhesion of the layers is promoted by use of an initiation layer.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for depositing low dielectric constant layers on a substrate.[0003]2. Description of the Related Art[0004]Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year / half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. The continued reduction in device geometries has generated a demand for inter layer dielectric films having lower dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits.[0005]Much research has been devoted to improving the per...

AI Technical Summary

Benefits of technology

The patent describes methods for depositing a memory device using a dense low-k dielectric film with terminal methyl groups. The method involves depositing the film by reacting a gas mixture containing a silicon precursor, a carbon precursor, and an oxygen precursor at a high temperature. The film is then opened and filled with a conductive material. The methods also involve sequentially depositing a silicon oxide layer with low carbon content and a carbon doped silicon oxide layer with high carbon content without plasma arcing. The variations in process conditions reduce the variation in DC bias of the powered electrode during processing. The methods can be used to form a memory device with improved performance.

Problems solved by technology

Processes for fabricating memory devices, however, feature subsequent high-temperature steps that cause the dielectric film to out-gas volatile species and shrink.

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