Method for Integrated Circuit Manufacturing and Mask Data Preparation Using Curvilinear Patterns

Abstract

A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.

Description

RELATED APPLICATIONS[0001]This application claims priority from U.S. Provisional Patent Application Ser. No. 61 / 392,477, filed Oct. 13, 2010, entitled “Method For Integrated Circuit Manufacturing and Mask Data Preparation Using Curvilinear Patterns”; which is hereby incorporated by reference for all purposes.BACKGROUND OF THE DISCLOSURE[0002]The present disclosure is related to the manufacturing of integrated circuits, and more particularly to the use of curvilinear patterns for making photomasks.[0003]In the production or manufacturing of semiconductor devices, such as integrated circuits, optical lithography may be used to fabricate the semiconductor devices. Optical lithography is a printing process in which a lithographic mask or photomask manufactured from a reticle is used to transfer patterns to a substrate such as a semiconductor or silicon wafer to create the integrated circuit (I.C.). Other substrates could include flat panel displays, holographic masks, or even other reti...

AI Technical Summary

Problems solved by technology

An example of an end-use limitation is defining the geometry of a transistor in a way in which it cannot sufficiently operate at the required supply voltage.

The design rule limitations reflect, among other things, the smallest dimensions that can be reliably fabricated.

As the critical dimensions of the circuit pattern become smaller and approach the resolution value of the exposure tool, the accurate transcription of the physical design to the actual circuit pattern developed on the resist layer becomes difficult.

However, because of

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