Policies for Shader Resource Allocation in a Shader Core

Abstract

A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention is generally directed to computing systems. More particularly, the present invention is directed to arbitration policies for allocating graphic processing unit resources among multiple pipeline inputs.[0003]2. Background Art[0004]The desire to use a graphics processing unit (GPU) for general computation has become much more pronounced recently due to the GPU's exemplary performance per unit power and / or cost. The computational capabilities for GPUs, generally, have grown at a rate exceeding that of the corresponding central processing unit (CPU) platforms. This growth, coupled with the explosion of the mobile computing market and its necessary supporting server / enterprise systems, has been used to provide a specified quality of desired user experience. Consequently, the combined use of CPUs and GPUs for executing workloads with data parallel content is becoming a volume technology.[0005]However, GPUs have tradition...

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Benefits of technology

[0014]What is needed, therefore, are improved arbitration methods and system...

Problems solved by technology

These constraints arose from the fact that GPUs did not have as rich a programming ecosystem as CPUs.

Their use, therefore, has been mostly limited to two dimensional (2D) and three dimensional (3D) graphics and a few leading edge multimedia applications, which are already accustomed to dealing with graphics and video application programming interfaces (APIs).

Although OpenCL and DirectCompute are a promising start, there are many hurdles remaining to creating an environment and ecosystem that allows the combination of the CPU and GPU to be used as fluidly as the CPU for most programming tasks.

Both of these arrangements, however, still include significant challenges associated with (i) separate memory systems, (ii) efficient scheduling, (iii) providing quality of service (QoS) guarantees between processes, (iv) programming model, and (v) compiling to multiple target instruction set architectures (ISAs)—all while minimizing power consumption.

While these external interfaces (e.g., chip to chip) negatively affect memory latency and power consumption for cooperating heterogeneous processors, the separate memory systems (i.e., separate address spaces) and driver managed shared memory create overhead that becomes unacceptable for fine grain offload.

By way of example, computational commands (e.g., physics or artificial intelligence commands) often cannot be sent to the GPU for execution.

This limitation exists because the CPU may relatively quickly require the results of the operations performed by these computational commands.

However, beca...

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