Unlock instant, AI-driven research and patent intelligence for your innovation.

Flash memory device and storage control method

a flash memory and control method technology, applied in the field of flash memory devices, can solve the problems of reducing the quality of flash memory, reducing the number of correctable bits of flash memory, and reducing the production efficiency of large-capacity nand flash memory, so as to increase the number of correctable bits and increase the number of

Inactive Publication Date: 2013-12-26
HITACHI LTD
View PDF2 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This solution extends the lifetime of NAND flash memory by effectively managing bit errors and maintaining performance without increasing ECC size, thereby enhancing the reliability and durability of SSDs.

Problems solved by technology

As structural miniaturization advances, large capacity NAND flash memory becomes more difficult to produce, which tends to lead to degradation of its quality, such as a lower upper limit on the number of rewrite processes and / or a shortened data retention period, and so on.
Further, as mentioned above, since there is a tendency of decrease in quality of flash memory, the MLC NAND flash memory lacks reliability, while having a large capacity.
Accordingly, it is difficult to adopt NAND flash memory as enterprise use without any measures being taken.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Flash memory device and storage control method
  • Flash memory device and storage control method
  • Flash memory device and storage control method

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0043]Firstly, a computer system according to a first embodiment will be described below.

[0044]FIG. 1 is a schematic structure figure of a computer system including an SSD according to a first embodiment.

[0045]The computer system comprises a higher-level device 10 and an SSD (Solid State Drive) 20 as an example of a flash memory device. The SSD 20 is communicatively coupled to the higher device 10 via a communication network (e.g., a LAN (Local Area Network)). For example, the higher-level device 10 may be a host computer or a controller of a storage system. In the following description, a host computer is taken as an example of the higher device 10, which will be denoted a host computer 10.

[0046]For example, the host computer 10 is an application server. The host computer 10 is installed with control software (not shown), which is executing on the host computer 10 for issuing control commands, such as write command or read command, to the SSD 20.

[0047]The SSD 20 includes an SSD con...

second embodiment

[0188]Next, a second embodiment will be described below. Incidentally, description will be made of the difference from the first embodiment.

[0189]In the first embodiment, segments of the SCM FM chip 222 are mapped to all of the physical pages included in the NAND FM chip 221. In the second embodiment, segments are mapped to particular physical pages, rather than all of the physical pages, i.e., to only valid physical pages storing important data (management information such as the address conversion table 1122). This allows a plurality of segments to be mapped to one particular physical page. In this manner, an increased capacity may be provided for storing error correction information of the data stored in a particular physical page. Consequently, a larger amount of error correction information may be transferred to the bit inversion circuit 2152 when reading data stored in a particular physical page, as compared with the first embodiment. That is, the correctable limit number of b...

third embodiment

[0193]Next, a third embodiment will be described below. Incidentally, description will be made of the difference from the first embodiment.

[0194]In the first embodiment, since no bit error occurs in the write data and the ECC for the write data (hereinafter, the write ECC) when data is written to the NAND FM chip 221 for the first time, the ECC circuit 2153 generates an initial value as error correction information. In this case, assuming that the initial value of error correction information is all zeros, the bit inversion circuit 2152 cannot correct bit errors by using the initial value of error correction information. Thus, for example, in a read process at a first point in time, if the total number of bit errors that have been occurred in the write data and the write ECC exceeds the correctable limit number by the ECC circuit 2153, uncorrectable errors result.

[0195]In contrast, in the third embodiment, when writing data to the NAND FM chip 221 for the first time, the ECC circuit...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

When writing data to a first-type FM part, an FM controller of a flash memory device (A1) generates a redundant code, and (A2) writes the data and the redundant code. when reading the written data, the flash memory controller (B1) reads the data and the redundant code, (B2) corrects any bit errors based on the redundant code, (B3) generates error correction information including positions of the bit errors occurring and values before the bit errors occurred, and (B4) writes the error correction information to a second-type FM part. Subsequently, when reading the data, the flash memory controller (C1) reads the data and the redundant code, (C2) reads the error correction information, (C3) corrects the data and the redundant code based on the error correction information, (C4) corrects any bit errors based on the corrected redundant code, (C5) updates the error correction information by adding, to the error correction information, positions of the corrected bit errors and values before the bit errors occurred, and (C6) writes the updated error correction information to the second-type FM part.

Description

TECHNICAL FIELD[0001]The present invention relates to flash memory devices including flash memory.BACKGROUND ART[0002]For example, NAND type flash memory (referred to as NAND flash memory), which is adopted in flash memory devices, such as SSDs, stores both data to be stored in NAND flash memory (hereinafter, store target data) and an error correcting code (e.g., ECC (Error Correcting Code)) for that store target data in order to ensure data reliability. In flash memory devices, when reading the store target data, if the number of bit errors in the store target data is within the number of bit errors that can be corrected by using an ECC (hereinafter, the number of correctable bits), then data correction is performed with the ECC and the data to be stored after the correction is read. Generally, as the data volume of an ECC stored with the store target data increases, the number of correctable bits becomes larger.[0003]As structural miniaturization advances, large capacity NAND flas...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): G11C29/04G06F11/16
CPCG06F11/1048
Inventor KOSEKI, HIDEYUKI
Owner HITACHI LTD