Transistor with embedded stress-inducing layers

Abstract

A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to the formation of a transistor device having embedded stress-inducing layers in the source and drain regions adjacent to the channel region.[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technol...

AI Technical Summary

Benefits of technology

The invention describes a method of making a transistor device, which includes steps of forming a gate electrode, adding an interlayer dielectric layer, making openings in the interlayer dielectric to reach the semiconductor layer, creating cavities in the semiconductor layer, and adding embedded semiconductor layers in the cavities. This method can produce either N-channel or P-channel FETs. Its technical effect is to provide a simplified description of the invention to facilitate understanding.

Problems solved by technology

The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.

However, some mechanisms for obtaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.

However, a particular problem arises when using the embedded silicon / germanium technique in the context of CMOS manufacturing and silicidated source / drain regions, as illustrated in FIGS. 1a and 1b.

For example, the drain and source regions may receive a metal silicide, such as nickel silicide, nickel platinum silicide and the like, thereby reducing the overall series resistance of the conductive path between the drain and source terminals and the intermediate channel region.

Since the silicon / germanium material does not properly grow at the STI edge, silicidation cannot properly be carried out.

Since the silicide material 15′ is not grown thickly enough, problems with contact landing arise.

Unconnected contacts that are formed in the contact opening 18′ formed above the sloped silicidated silicon / germanium compound 16′ may, therefore, cause device failures.

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