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Mixed mode compensation circuit

a compensation circuit and mixed mode technology, applied in the field of power converters, can solve the problems of inability to accurately control the small current, the inability to completely integrate the large capacitors cb>1/b> and cb>2/b> and the inability to fully integrate the large capacitors into the control i

Inactive Publication Date: 2016-11-10
RICHTEK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The mixed mode compensation circuit effectively reduces the need for large capacitors, simplifies chip design, and enhances the power converter's ability to rapidly respond to load transients, reducing voltage drops and overshoots while minimizing chip area and costs.

Problems solved by technology

Generally speaking, the gm type compensation circuit 14 is easier to be integrated into a control IC, while this type of solutions also has many limitations.
Under consideration of costs and chip area, it is much difficult to integrate the large capacitors C1 and C2 into the control IC completely.
However, the large capacitors C1 and C2 satisfying the requirements cannot be implemented in a control IC, the control IC is required a pin to be connected to external large capacitors C1 and C2.
If it is desired to shrink the capacitors C1 and C2 so that they can be integrated into a control IC, then it needs the current Icomp to be reduced to the nanoampere level or the picoampere level; however, such a small current is much sensitive to the process and cannot be controlled accurately, so it is difficult to integrate the large capacitors C1 and C2 into a control IC.
Although these digital compensation circuits can be integrated into the control IC of a PFC power converter, usually a complex digital signal processing (DSP) algorithm is needed and thus a large chip area is required, resulting in increased costs and chip size.
On the other hand, the slowly varying signal Vcomp will make a power converter unable to rapidly respond to a load transient, resulting in a large voltage drop or overshoot of the output voltage Vo.

Method used

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Examples

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first embodiment

[0046]FIG. 4 is a circuit diagram of a first embodiment for the mixed mode compensation circuit 20 shown in FIG. 3A. In order to realize the first pole of a low frequency, the digital signal generator 22 and the DAC 24 are used to simulate the transconductance amplifier 16 of the gm type compensation circuit 14 shown in FIG. 2. In the digital signal generator 22 shown in FIG. 4, a comparator 30 compares the feedback signal Vfb1 with the reference signal Vref1 to generate a comparison signal Sc1, an inverter 32 inverts the comparison signal Sc1 to generate a signal Sc2 for a controller 42, an oscillator 40 provides a clock signal Clk for the controller 42 and an up / down counter 44, and the controller 42 samples the signal Sc2 responsive to the clock signal Clk to assert control signals Up and Down for the up / down counter 44 to adjust the digital signal Sd. When the sampling result indicates that the feedback signal Vfb1 is greater than the reference signal Vref1, the controller 42 as...

second embodiment

[0051]FIG. 7 is a circuit diagram of a second embodiment for the mixed mode compensation circuit 20 shown in FIG. 3A. In the digital signal generator 22, a multiplexer 60 is configured to switch a threshold VH1, a threshold VH2, the reference signal Vref1, a threshold VL2 and a threshold VL1 in turn to a non-inverting input terminal of a comparator 62 responsive to pulse signals Sp1-Sp5, respectively, where VH1>VH2>Vref1>VL2>VL1, the comparator 62 has an inverting input terminal to receive the feedback signal Vfb1 and compares the feedback signal Vfb1 with VH1, VH2, Vref1, VL1 and VL2 one by one to generate a comparison signal for the controller 42, and the controller 42 samples the comparison signal from the comparator 62 responsive to a clock signal Clk and the pulse signals Sp1-Sp5, and asserts control signals Up and Down for the up / down counter 44 according to the sampling result so as to increase or decrease the digital signal Sd. The controller 42 also identifies whether the f...

third embodiment

[0054]FIG. 10 is a circuit diagram of a third embodiment for the mixed mode compensation circuit 20 shown in FIG. 3A. In the digital signal generator 22, a comparator 70 compares the feedback signal Vfb1 with a threshold VH1 to generate a comparison signal SB1, a comparator 72 compares the feedback signal Vfb1 with a threshold VH2 to generate a comparison signal SB2, a comparator 74 compares the feedback signal Vfb1 with the reference signal Vref1 to generate a comparison signal SB3, a comparator 76 compares the feedback signal Vfb1 with a threshold VL2 to generate a comparison signal SB4, a comparator 78 compares the feedback signal Vfb1 with a threshold VL1 to generate a comparison signal SB5, a controller 80 selects one of clock signals Clk1, Clk2, Clk3, Clk4 and Clk5 as the clock signal Clk provided to an up / down counter 44 according to the comparison signals SB1, SB2, SB3, SB4 and SB5 in the way that when the feedback signal Vfb1 is greater than the maximum threshold VH1 or sma...

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PUM

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Abstract

A mixed mode compensation circuit for a power converter generate a digital signal according to a reference signal and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.

Description

CROSS REFERENCE[0001]The present invention is a continuation-in-part application of U.S. Ser. No. 13 / 672,125, filed on Nov. 8, 2012.BACKGROUND OF THE INVENTION[0002]1. Field of Invention[0003]The present invention is related generally to a power converter and, more particularly, to a compensation circuit and method for a power converter.[0004]2. Description of Related Art[0005]A feedback loop of a power converter needs a compensation circuit to compensate the phase margin for stability of the feedback loop. Conventional analog compensation circuits include an EA type compensation circuit 10 as shown in FIG. 1 or a gm type compensation circuit 14 as shown in FIG. 2. Referring to FIG. 1, the EA type compensation circuit 10 includes an error amplifier 12, a capacitor C1 and a resistor R3 serially connected between an inverting input terminal and an output terminal of the error amplifier 12, and a resistor R4 parallel connected with the serially connected capacitor C1 and resistor R3. T...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G05F1/10H03M1/38
CPCH03M1/38G05F1/10H02M3/157H02M1/0025
Inventor TANG, CHIEN-FUPAN, JIUN-HUNGCHEN, ISAAC Y.
Owner RICHTEK TECH