Buried word line structure and method of making the same

Abstract

A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source / drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a buried word line structure and a method of fabricating the same, and more particularly to a buried word line structure which reduces the gate-induced drain leakage (GIDL) problem.2. Description of the Prior Art[0002]As device geometries shrink, reliability problems due to gate induced drain leakage forces the integrated circuit to operate at voltages which are lower than desired for best performance. When the device is biased, gate induced drain leakage results from the generation of electron-hole pairs in the surface of the depletion region of a transistor along the area where the gate conductor overlaps the drain diffusion region, such that the drain potential is more positive than the gate potential.[0003]DRAM is a commonly-seen memory and is widely used in computers and other electronic appliances. DRAM includes a memory cell array composed of capacitors to store data. In a DRAM array, g...

AI Technical Summary

Benefits of technology

The buried word line structure effectively lowers gate-induced drain leakage, enhancing data retention time and allowing for optimal voltage operation in DRAM by reducing electric field formation between the word line and source / drain regions.

Problems solved by technology

As device geometries shrink, reliability problems due to gate induced drain leakage forces the integrated circuit to operate at voltages which are lower than desired for best performance.

In a DRAM array, gate induced drain leakage degrades data retention time.

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