Method and structure of forming finfet contact

Abstract

Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source / drain region layer and source / drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source / drain contact. The source / drain contact is disposed directly on and contacting the entire source / drain region layer, and at a vertical level thereabove, the source / drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source / drain region layer. A method uses a reverse contact mask to form a shape of the source / drain contact into an inverted “T” shape.

Description

BACKGROUND OF THE INVENTION[0001]The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating FET semiconductor devices.[0002]Self-aligning contacts (SAC) are typically used in semiconductor fabrication technology for CMOS (complementary metal-oxide-semiconductor) technology below 14 nm nodes, due to limited available space for placing transistor source / drain contacts. To place transistors as close as possible to each other, a source / drain contact of an FET transistor, for example, is merged with a source / drain contact of another adjacent FET transistor, thereby minimizing the distance between the two transistors on a substrate. However, the merged source / drain contact will be located very close to an adjacent gate of each of the two adjacent transistors. A thin spacer insulating material may be the only structure that separates the conductive source / drain contact and gate. This semiconductor structure, i.e., the so...

AI Technical Summary

Benefits of technology

This approach effectively reduces parasitic capacitance while maintaining negligible resistance increase, improving the performance of semiconductor circuits by optimizing the layout of source / drain contacts in FET structures.

Problems solved by technology

Self-aligning contacts (SAC) are typically used in semiconductor fabrication technology for CMOS (complementary metal-oxide-semiconductor) technology below 14 nm nodes, due to limited available space for placing transistor source / drain contacts.

This is an unintended capacitor with parasitic capacitance that increases power consumption and slows down the speed of a semiconductor circuit.

The increased parasitic capacitance is undesirable for most circuit designs.

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