Metal zero contact via redundancy on output nodes and inset power rail architecture

Abstract

A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and / or metal one extension layers are placed in the identified external path.

Description

BACKGROUNDDescription of the Relevant Art[0001]As both semiconductor manufacturing processes advance and on-die geometric dimensions reduce, semiconductor chips provide more functionality and performance while consuming less space. While many advances have been made, design issues still arise with modern techniques in processing and integrated circuit design that limit potential benefits. For example, capacitive coupling, electro migration, leakage currents and processing yield are some issues which affect the placement of devices and the routing of signals across an entire die of a semiconductor chip. Additionally, as the transistor dimensions decrease, the short channel effects increase. Other examples of short channel effects other than leakage current are latch-up effects, drain-induced barrier lowering (DIBL), punch-through, performance dependency on temperature, impact ionization, and parasitic capacitance to the silicon substrate and to the wells used for the source and drain...

AI Technical Summary

Benefits of technology

The patent text discusses the challenges in designing semiconductor chips with non-planar devices, such as tri-gate transistors and fin field effect transistors, and the impact of resistance values and leakage currents on performance. The text describes methods and systems for creating layouts for non-planar cells with redundancy in output contacts and power contacts. The technical effects of the patent text include efficient methods and systems for creating layouts for non-planar cells with redundancy in output contacts and power contacts, as well as improved performance and reliability of semiconductor chips.

Problems solved by technology

While many advances have been made, design issues still arise with modern techniques in processing and integrated circuit design that limit potential benefits.

For example, capacitive coupling, electro migration, leakage currents and processing yield are some issues which affect the placement of devices and the routing of signals across an entire die of a semiconductor chip.

Thus, these issues have the potential to delay completion of the design and affect the time to market.

The processing steps for non-planar devices (transistors) and other components within the cell layouts are more complex than the processing steps for planar devices.

In either case, due to the complexity of the semiconductor fabrication processing steps for non-planar devices and the decreasing dimensions for the non-planar devices, resistance values increase.

A relatively large output time constant decreases an amount of time within a clock cycle to perform desired functionality, and so, performance decreases.

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