Semiconductor integrated circuit
a semiconductor and integrated circuit technology, applied in the direction of individual semiconductor device testing, semiconductor/solid-state device testing/measurement, instruments, etc., can solve the problems of high cost, large size of semiconductor integrated circuits, and accompanied substrate types by high cost, so as to reduce costs
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embodiment 1
(Embodiment 1)
[0069]FIG. 1 is a partial plane view showing an example of a structure of a semiconductor integrated circuit according to Embodiment 1 of the invention by seeing through a seal member, FIG. 2 is a sectional view showing the example of the structure of the semiconductor integrated circuit shown in FIG. 1, FIG. 3 is a block diagram showing an example of a system of the semiconductor integrated circuit shown in FIG. 1, FIG. 4 is a sectional view showing an example of a structure of a lead frame used in integrating the semiconductor integrated circuit shown in FIG. 1, FIG. 5 is a sectional view showing an example of a structure in finishing die bonding, FIG. 6 is a sectional view showing an example of a structure in finishing wire bonding, FIG. 7 is a sectional view showing an example of a structure in finishing to seal by a resin, FIG. 8 is an enlarged partial plane view showing an example of a structure before bonding in wire bonding, FIG. 9 is an enlarged partial plane ...
embodiment 2
(Embodiment 2)
[0139]FIG. 19 is a sectional view showing an example of a structure of a semiconductor integrated circuit according to Embodiment 2 of the invention, FIG. 20 is a bottom view showing an example of a structure of the semiconductor apparatus shown in FIG. 19 and FIG. 21 is a partial plane view showing an example of a relationship between a lead array and an external terminal array in the semiconductor integrated circuit shown in FIG. 19.
[0140]The semiconductor integrated circuit of Embodiment 2 shown in FIG. 19 is SIP 11 in which the microcomputer chip 3 and SDRAM 2 are arranged to align laterally similar to SIP 1 of Embodiment 1, and a difference from SIP 1 of Embodiment 1 resides in that an outer shape of the semiconductor integrated circuit is constituted not by the QFP type but by a QFN (Quad Flat Non-leaded Package) type.
[0141]That is, SIP 11 of Embodiment 2 is a semiconductor package of the QFN type and as shown by FIG. 20, a plurality of bump electrodes 12 constit...
embodiment 3
(Embodiment 3)
[0146]FIG. 22 is a conceptual diagram showing a total constitution of a semiconductor integrated circuit of Embodiment 3 according to the invention and FIG. 23 is a conceptual diagram showing an arrangement of ASIC and SDRAM in a package in the semiconductor integrated circuit of Embodiment 3.
[0147]First, an example of a constitution of a semiconductor integrated circuit of Embodiment 3 will be explained. The semiconductor integrated circuit of Embodiment 3 is considered to be SIP 102 mounted with, for example, ASIC (system chip) 100 and SDRAM (memory chip) 101 in a single package (for example, QFP) and is constituted by ASIC (Application Specific Integrated Circuit) 100 including an analog circuit 103, a circuit memory 104, CPU (Central Processing Unit) 105, a logic circuit 106, an IO (Input / Output) portion 107, MBIST (Memory Built In Self Test) 108, SDRAMBIST (Synchronous Dynamic Random Access Memory Built In Self Test) 109 and SDRAM (Synchronous Dynamic Random Acces...
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