Semiconductor device performing refresh operation
a technology of a semiconductor device and a refresh operation, which is applied in the direction of semiconductor devices, digital storage, instruments, etc., can solve the problems of unnecessarily increasing current consumption, wasting current consumption, and malfunctioning of the dram chip
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first embodiment
[0021]A semiconductor device according to the present embodiment has two DRAM (Dynamic Random Access Memory) chips and one SOC (System-on-a-Chip) chip. Further, in the present embodiment, these three semiconductor chips are mounted in one package using a TSV (Through Silicon Via) technology.
[0022]Referring now to FIG. 1A, the semiconductor device 1 has two DRAM chips 10_0 and 10_1, an SOC chip 11, and a package substrate 3. The SOC chip 11 and two DRAM chips 10_0 and 10_1 are stacked on the package substrate 3 and covered (encapsulated) by an encapsulation resin 4. That is, the plurality of semiconductor chips (two DRAM chips 10_0 and 10_1 and SOC chip 11) are mounted on the package substrate 3. The plurality of semiconductor chips and package substrate 3 are encapsulated by the same encapsulation resin 4 (resin).
[0023]External connection terminals 2 are formed on a surface of the package substrate 3 on a side opposite to a surface covered by the encapsulation resin 4.
[0024]Each of ...
second embodiment
[0111]In FIG. 7, the same reference numerals are given to the same elements as those of FIG. 5, and the explanation is not repeated.
[0112]In the present embodiment, a configuration in which the output result of a temperature sensor 30_0 and output result of a temperature sensor 30_1 are shared between the DRAM chips 10_0 and 10_1 by using a single signal line will be described.
[0113]In the present embodiment, the refresh controller 40_0 has an OSC unit 41_0, an inverter circuit 43_0, a NAND circuit 44_0, dividing circuits 45_0 and 47_0, a multiplexer 46_0, a PMOS transistor (p-channel metal-oxide semiconductor field-effect transistor) 48_0, and an NMOS transistor (n-channel metal-oxide semiconductor field-effect transistor) 49_0.
[0114]The PMOS transistor 48_0 has a source terminal connected to a drive power supply, a gate terminal connected to a ground power supply, and a drain terminal connected to a node N1. When the source terminal and drain terminal are in a conductive state, th...
third embodiment
[0126]Turning to FIG. 8, the semiconductor device 1 has the DRAM chips 10 (10_0, 10_1) and SOC chip 11.
[0127]In the present embodiment, the DRAM chips 10 (10_0, 10_1) which are the first semiconductors each have the refresh controller 40, control logic unit 24, and row address buffer 25. That is, the DRAM chip 10_0 has the refresh controller 40_0, control logic unit 24_0, and row address buffer 25_0, and the DRAM chip 10_1 has the refresh controller 40_1, control logic unit 24_1, and row address buffer 25_1.
[0128]The SOC chip 11 (third semiconductor chip) is a controller controlling, e.g., the DRAM chip 10 and has a temperature sensor 31. The SOC chip 11 is also a control chip that outputs address signals and command signals to the DRAM chip 10.
[0129]The temperature sensor 31 has the same configuration as that of the temperature sensor 30 in the first and second embodiments.
[0130]In the present embodiment, the refresh controller 40 (40_0, 40_1) changes the refresh period of the DRAM...
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