High performance surface mount electrical interconnect

Abstract

A method of forming an interconnect assembly including forming a substrate with a plurality of through holes extending from a first major surface to a second major surface. A plurality of recesses are formed in the second major surface of the substrate that at least partially overlap with the plurality of through holes. The recesses have a cross-sectional area greater than a cross-sectional area of the through holes. At least one discrete contact member is inserted in a plurality of the through holes. The contact members include proximal ends extending into the recesses, distal ends extending above the first major surface, and intermediate portions engaged with an engagement region of the substrate located between the first major surface and the recesses. Retention members at least partially deposited in the recesses bond to the proximal ends to retain the contact members in the through holes.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a national stage application under 35 U.S.C. §371 of International Application No. PCT / US2010 / 036043, titled HIGH PERFORMANCE SURFACE MOUNT ELECTRICAL INTERCONNECT, filed May 25, 2010, which claims priority to U.S. Provisional Application No. 61 / 181,937, filed May 28, 2009, both of which are hereby incorporated by reference in their entireties.TECHNICAL FIELD[0002]The present application relates to a high performance electrical interconnect assembly between an integrated circuit and a printed circuit assembly.BACKGROUND OF THE INVENTION[0003]Traditional integrated circuit (IC) sockets are generally constructed of an injection molded plastic insulator housing which has stamped and formed copper alloy contact members stitched or inserted into designated positions within the housing. The designated positions in the insulator housing are typically shaped to accept and retain the contact members. The assembled socket body i...

AI Technical Summary

Benefits of technology

[0012]In one embodiment, the contact members can be simple beam structures made of conventional materials, but omit the normal retention features that add parasitic mass and distort or degrade the integrity of the signal as it passes through the contact member. This approach provides a reliable connection to the package terminals and creates a platform to add electrical and mechanical enhancements to the substrate of the socket to address the challenges of next generation interconnect requirements. The lack of contact member retention features greatly reduces the complexity of the contact members and the tooling required to produce them.

[0023]In one embodiment, a layer of dielectric material is bonded to the first surface of the substrate. The layer preferably has a thickness less than a height of the distal ends of the contact members. The layer can be used to limit deflection of the distal end and to provide a barrier between adjacent contact members to prevent inadvertent contact.

Problems solved by technology

As systems advance to next generation architectures, these traditional devices have reached mechanical and electrical limitations that mandate alternate approaches.

As the terminal pitch reduces, however, the surface area available to place a contact is also reduced, which limits the space available to locate a spring or a contact member that can deflect without touching a neighbor.

Thinner walls increase the difficulty of molding as well as the latent stress in the molded housing that can cause warping due to heat applied during solder reflow.

Long contact members, however, tend to reduce the electrical performance of the connection by creating a parasitic effect that impacts the signal as it travels through the contact.

Also, the small space between contact members can cause distortion as a nearby contact member influences a neighboring contact member, which is known as cross talk.

Traditional sockets and methods of fabricating the same are able to meet the mechanical compliance requirements of today's needs, but they have reached an electrical performance limit.

Next generation systems will operate above 5 GHz and beyond and the existing interconnects will not achieve acceptable performance levels without significant revision.

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