Embedded semiconductor device package and method of manufacturing thereof

Abstract

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Description

BACKGROUND OF THE INVENTION[0001]Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to an embedded package structure having power overlay (POL) interconnects that form all electrical and thermal interconnections in the package.[0002]Surface-mount technology is a method for constructing electronic circuits in which surface mount components or packages are mounted directly onto the surface of printed circuit boards (PCBs) or other similar external circuits. In the industry, surface-mount technology has replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board.[0003]One common technique for surface-mounting a semiconductor device (or a multi-chip module) is to provide a package structure in which the device / module is encapsulated within an embedding compound. The package manufacturing process begins with placement of one or more semicondu...

AI Technical Summary

Benefits of technology

The solution enhances reliability, reduces manufacturing costs, and enables miniaturization by forming robust electrical and thermal connections within the package, improving system-level performance and compatibility with surface mount technology.

Problems solved by technology

For example, the encapsulants and embedding compounds that are generally used have limited reliability when moisture sensitivity level (MSL)-qualification is required, due to their poor fracture toughness and high moisture uptake.

Additionally, the encapsulants / embedding compounds typically used can be expensive to procure and slow and time consuming to apply.

Furthermore, and with particular regard to packaging power devices / modules, the soldering operation typically employed for electrically and thermally connecting the POL sub-module to the ceramic substrate can be costly and time consuming, with the additional temperature excursion required by soldering also adversely affecting module reliability.

Still further, the inclusion of the ceramic substrate in the POL package places limits on an achievable reduction in size and thickness of the POL package (i.e., miniaturization) due to the size / thickness of the ceramic substrate.

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