Self-aligned low resistance buried contact process

Abstract

A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

Description

FIELD OF THE INVENTIONThis invention relates to semi-conductor integrated circuits, and more specifically to the creation of reliable buried contacts between a transistor element and a remote diffusion area. The invention has particular applicability to the fabrication of integrated memory circuits.BACKGROUND OF THE INVENTIONBuried contacts are used in the fabrication of integrated circuits in order to establish current pathways through the underlying substrate rather than on the top surface of the circuit. Buried contacts ensure electrical isolation from other parts of the circuit, and leave the top surface free for use in establishing other connections and outside contacts giving access to the circuit.For instance, in the fabrication of Static Random Access Memories (SRAMs), a buried contact is used to link the gate of one transistor to the drain of another in a paired transistor memory cell, as explained in U.S. Pat. No. 5,064,776 Roberts.In the fabrication of Dynamic Random Acce...

AI Technical Summary

Benefits of technology

The principal and secondary objects of this invention are to provide a reliable technique for diffusing buried contacts through a relatively small window while avoiding the formation of parasitic MOS devices between the buried contact and the remote source or drain diffusion area; and to do so with a limited number of masking steps.

Problems solved by technology

Insufficient diffusion or implantation leaving too large a spacing between the edge of the buried contact and the outer edge of the polysilicon defining the source or drain may result in the creation of a parasitic MOS device having a relatively high threshold voltage (Vt) between the buried contact and the remote source or drain location.

This parasitic MOS device may increase the buried contact resistance and degrade the circuit performance.

Various techniques based on successive diffusion or punch-through implantations which have been used in the past require multiple masking steps which increase the fabrication complexity, processing time and cost.

Images