Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Sealed stacked arrangement of semiconductor devices

a semiconductor device and stacking technology, applied in semiconductor devices, semiconductor/solid-state device details, instruments, etc., can solve the problems of deteriorating product yield, complicated manufacturing process, and inability to constitute a package using the same size of sub-chips formed in the same manufacturing process, and achieves effective chip mounting, large memory capacity, and the effect of avoiding the loss of heat radiation characteristic of the package and product yield

Inactive Publication Date: 2002-02-05
ELPIDA MEMORY INC
View PDF44 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

It is the first object of the present invention to provide an effective chip mounting method capable of mounting plural sub chips of the same size without sacrificing the heat radiation characteristic of a package and the product yield.
It is the third object of the present invention to realize a DRAM package having a memory capacity plural times that of a package of about the same size and comprising a single DRAM chip and thereby expand the limit of memory capacity of DRAM chips, etc.
According to the above means it is possible to provide an effective chip mounting method capable of mounting plural sub chips of the same size without sacrificing the heat radiation characteristic of the package and the product yield. Besides, it is possible to attain large memory capacity and low power consumption of the DRAM package and simplify the manufacturing process for the package. Moreover, it is possible to realize a DRAM package having a memory capacity plural times that of a package comprising a single DRAM chip and thereby expand the limit of memory capacity of DRAM chips; at the same time it is possible to enhance the packaging efficiency of a memory system having a DRAM package as a basic configuration and reduce the cost thereof. Further, it is possible to utilize partial DRAM chips without waste and enhance a substantial product yield of DRAM chips, etc.

Problems solved by technology

However, with progress of higher integration density and larger capacity of semiconductor chips, the present inventors found out that the following problems were involved in the foregoing chip mounting methods.
Therefore, it is impossible to constitute a package using the same size of sub chips formed in the same manufacturing process, like a DRAM chip for example.
In all of these methods, moreover, the manufacturing process is complicated and the product yield is deteriorated in comparison with, for example, the conventional packaging method involving direct wire bonding to a lead frame.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Sealed stacked arrangement of semiconductor devices
  • Sealed stacked arrangement of semiconductor devices
  • Sealed stacked arrangement of semiconductor devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

1. 128M DRAM Package according to Double Chip Packaging Method

1.1. Outline of DRAM Package

FIG. 1 is a block diagram showing an example of a 128M ("M" or "mega" is assumed equal to the twentieth power of 2 herein) DRAM package according to the present invention, and FIG. 2 is a timing chart in the said DRAM package. With reference to these figures, an outline of this DRAM package and an explanation of a chip selecting method will first be given below. The chip mounting method according to the present invention will herein be designated a double chip packaging method. For a specific description of the double chip packaging method and features thereof, see "1.4. Package Form of DRAM Package."

1.1.1. Block Configuration

A DRAM package 1 according to this embodiment includes two DRAM sub chips 1A and 1B. These sub chips each have a memory capacity of 64 mega. Write data and read data are inputted or outputted each in the unit of one bit through a data input terminal Din or a data output te...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Description

BACKGROUND OF THE INVENTIONThe present invention relates to a semiconductor device and a method for manufacturing the same. For example, the present invention is concerned with a DRAM package (a semiconductor device with one or plural DRAM chips mounted thereon will hereinafter be referred to herein as "DRAM package") comprising plural DRAM (Dynamic Random Access Memory) chips (a semiconductor chip capable of functioning as DRAM will hereinafter be referred to herein as "DRAM chip"), as well as a technique which is particularly useful in producing such DRAM package.A DRAM chip having as a basic configuration a memory array comprising lattice-like arranged dynamic memory cells as well as a DRAM package having such DRAM chip as a basic configuration are known. In the conventional DRAM package, usually, one DRAM chip is mounted thereon and bonding pads used therein are connected to corresponding leads of a lead frame integral with external terminals.As to the DRAM package carrying a si...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(United States)
IPC IPC(8): H01L23/48H01L23/495G11C5/00H01L25/065H01L25/00H01L23/50H01L25/04H01L25/07H01L25/18H01L27/10
CPCG11C5/00G11C5/06H01L23/4951H01L23/49537H01L23/49575H01L24/06H01L25/0652G11C5/02H01L2924/1306H01L24/45H01L2224/0401H01L2224/04042H01L2224/06136H01L2224/32245H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/4554H01L2224/4569H01L2224/48091H01L2224/48247H01L2224/4826H01L2224/49171H01L2224/73215H01L2924/01006H01L2924/01013H01L2924/01014H01L2924/01015H01L2924/01029H01L2924/01033H01L2924/01039H01L2924/01073H01L2924/01079H01L2924/01082H01L2924/014H01L2924/13091H01L2924/14H01L2224/05554H01L2224/49175H01L24/48H01L2924/01005H01L2924/01019H01L2924/01023H01L2924/01043H01L2924/01047H01L2924/01055H01L24/49H01L2224/73265H01L2224/48137H01L2924/00014H01L2924/00H01L2924/00012H01L2924/181H01L2924/12042H01L2224/45H01L2224/45565H01L2225/1029H01L2924/07802H01L25/065H01L23/50
Inventor OGUCHI, SATOSHIISHIHARA, MASAMICHIITO, KAZUYAMURAKAMI, GENANJOH, ICHIROSAKUTA, TOSHIYUKIYAMAGUCHI, YASUNORIKASAMA, YASUHIROUDAGAWA, TETSUMOMOSE, EIJIMATSUNO, YOUICHISATOH, HIROSHINOZOE, ATSUSI
Owner ELPIDA MEMORY INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products