12 results about "Drain efficiency" patented technology

The invention relates to the technical field of power amplifiers and discloses a design method for a dual-band high-efficiency power amplifier with a wide frequency ratio, comprising: establishing a first high-efficiency mode based on a drain voltage on a drain current plane of a transistor and a drain current tuned by a second harmonic source impedance, and obtaining a fundamental output power and a drain efficiency in the mode; establishing a second high-efficiency mode based on a drain voltage on a drain current plane of a transistor and a drain current tuned by a second harmonic source impedance; the design method for the dual-band high-efficiency power amplifier with a wide frequency ratio obtains an optimal drain impedance design space according to the fundamental output power and the drain efficiency in the two modes by designing the first high-efficiency mode and the second high-efficiency mode, so as to facilitate the selection of two wide-frequency ratio working frequency bands based on the optimal drain impedance design space and meet the design requirements of the dual-band high-efficiency power amplifier.

The invention discloses a continuous load modulation balanced power amplifier based on a harmonic suppression coupler, equipment and a method. The amplifier comprises a power divider, a power divider and a harmonic suppression coupler, the first branch comprises a first input matching network, a first transistor and a first output matching network in sequence; the balance branch comprises a phase compensation line, a front matching network, an input end 3dB directional orthogonal coupler, a second branch, a third branch and an output end 3dB directional orthogonal coupler, and the second branch comprises a second input matching network, a second transistor and a second output matching network which are connected in sequence; the third branch comprises a third input matching network, a third transistor and a third output matching network which are connected in sequence; and post-matching the network. According to the continuous load modulation balanced power amplifier, the design of continuous mode impedance of the continuous load modulation balanced power amplifier and the improvement of the overall drain efficiency are realized by adopting the harmonic suppression coupler, so that the full working frequency band can work efficiently, and the design of a corresponding matching network is simplified.

The present application relates to the technical field of load-pull test, and discloses a load-pull test method, system and storage medium for a manual tuner, wherein the method comprises: in response to a load-pull test instruction of a target user, controlling the signal source to turn on, performing calculations based on the power value of the power meter and the drain current value of the device under test, obtaining the drain efficiency of the device under test, and then obtaining the S parameter data on both sides of the TRL calibration fixture, the S parameter data of the attenuator, the S parameter data of the manual tuner and the reflection coefficient of the attenuator, and finally performing calculations based on the S parameter data on both sides of the TRL calibration fixture, the S parameter data of the attenuator, the S parameter data of the manual tuner, the reflection coefficient of the attenuator and the power value of the power meter, obtaining the power value of the device under test. The power value and drain efficiency of the device under test can be accurately tested, thereby improving the effect of the load-pull test.

The application discloses a high-efficiency broadband radio frequency power amplifier based on an open resonant ring and a design method thereof, and at least comprises a broadband input matching network, a transistor circuit and an output matching network, wherein the output matching network is provided with at least an open resonant ring second harmonic matching network and a broadband fundamental wave matching network, and the open resonant ring second harmonic matching network is composed of a two-port rectangular double-loop open resonant ring. By using the low-resistance characteristic of the open resonant ring in the stop band, the application can match the second harmonic at the output end, and the second harmonic matching and the fundamental wave matching are carried out separately, so that the second harmonic and the fundamental wave can be well matched to the optimal output impedance at the same time, thereby improving the drain efficiency and the working bandwidth.

The invention discloses an EF type radio frequency power amplifier circuit which comprises a transistor, an EF type matching network is connected between a drain electrode of the transistor and an output matching network, the EF type matching network comprises an E type matching network and multiple F type matching networks, and the multiple F type matching networks are used for controlling second harmonic impedance and third harmonic impedance. The multiple F-type matching network comprises a first parallel inductor, a second parallel capacitor and a series resonance network composed of the second parallel inductor and a third parallel capacitor, and the second parallel capacitor is connected with the series resonance network composed of the second parallel inductor and the third parallel capacitor in parallel and then connected with the first parallel inductor in series. A novel EF-type circuit is formed by innovatively combining an E-type matching network with multiple F-type matching networks. The high drain electrode efficiency can be achieved while the peak voltage swing at the two ends of the device is effectively controlled, the risk that the device is broken down is reduced, and meanwhile harmonic waves can be effectively restrained.

The application discloses an efficiency-enhanced two-stage driving stacked four-frequency multiplier, comprising a differential signal generating circuit, a quadrature signal generating circuit and a double-push frequency multiplier. The quadrature signal generating circuit avoids the use of a stage-to-stage balun, maximally reduces loss and improves the efficiency of the frequency multiplier. The double-push frequency multiplier adopts a series structure, a series resonance circuit is added to the input end of the first-stage double-push frequency multiplier, the output power of a transistor and the second-harmonic suppression capability are improved, the first stage is biased in A and B classes, and the source and the gate of the second-stage double-push frequency multiplier are driven. The stacked double-driving structure reduces the driving power required by the second stage to the first stage, realizes the improvement of transconductance, multiplexes current through stacking, reduces direct-current power consumption, and the second-stage double-push frequency multiplier is biased in C class, so that the output power and the drain efficiency are improved. The application has the characteristics of high drain efficiency, good harmonic suppression capability and output power.

A multi-band Doherty power amplifier (DPA) is provided. A dual-band Doherty power amplifier (DB-DPA) is based on a 3-way architecture and comprises a main amplifier for each band and an auxiliary amplifier handling both bands. The 3-Way DB-DPA improves the average drain efficiency in concurrent dual-band operation compared to the traditional 2-Way DB-DPA, by avoiding early clipping in the main amplifiers, while benefiting from load-pulling from the auxiliary power amplifier.

The application relates to a design method of a wideband asymmetric quasi-balanced DPA with an enlarged backoff range, which comprises the following steps: establishing the architecture of the wideband asymmetric quasi-balanced DPA, establishing the equivalent circuit model of the wideband asymmetric quasi-balanced DPA, and obtaining the mathematical relationship between voltage and current; adopting a linear current model as an excitation signal to determine the load impedance, output power and drain efficiency under different normalized input levels; setting the load impedance of the main power amplifier and the auxiliary power amplifier to be equal when the output power is saturated, and obtaining the adjustable proportional coefficient of the loaded load; setting the voltage of the main power amplifier to be equal after the voltage saturation, and obtaining the relationship between the current ratio of the auxiliary power amplifier and the normalized input starting level; obtaining the relationship between the output power backoff ratio and the normalized input starting level; and optimizing the isolation port load of the output coupler and the direct current bias combination of the main power amplifier and the auxiliary power amplifier in the target working frequency band to meet the efficiency requirement under the set output power backoff ratio.

The invention discloses an efficiency enhanced two-stage driving stacked frequency quadrupler. The frequency quadrupler comprises a differential signal generating circuit, an orthogonal signal generating circuit and a double-push frequency multiplier, through the orthogonal signal generation circuit, the use of an inter-stage balun is avoided, the loss is reduced to the maximum extent, and the efficiency of the frequency multiplier is improved; the double-push-type frequency multiplier adopts a series structure, a series resonance circuit is added to the input end of the first-stage double-push-type frequency multiplier, the output power and the second harmonic suppression capability of a transistor are improved, the first stage is biased in A and B classes, and the output drives the source electrode and the grid electrode of the second-stage double-push-type frequency multiplier; the stacked dual-drive structure enables the driving power required by the second stage to the first stage to be reduced, and the transconductance is improved; the current is multiplexed through stacking, and the direct-current power consumption is reduced; the second-stage double-push frequency multiplier is biased in class C, so that the output power and the drain efficiency are improved. According to the invention, the characteristics of high drain electrode efficiency and good harmonic suppression capability and output power are embodied.

The invention provides a radio frequency power amplifier based on a Balun-like ring resonance structure and a design method thereof, the radio frequency power amplifier comprises an input matching network, a transistor circuit, a bias circuit and an output matching network, the bias circuit comprises a gate bias circuit and a drain bias circuit; the output matching network comprises a harmonic control network and a fundamental wave matching network, the harmonic control network adopts a Balun-like four-port annular resonant structure, and the fundamental wave matching network adopts a T-shaped microstrip line network and comprises a first T-shaped microstrip line fundamental wave matching network and a second T-shaped microstrip line fundamental wave matching network. According to the technology, a novel Balun-like annular resonance structure is used, the filtering characteristic of the structure is utilized, a reactance component is added to an isolation port, through setting of port impedance, a fundamental wave frequency band is made to be a pass band, a second harmonic frequency band is made to be a stop band, second harmonics at the output end are restrained, and the efficiency of a drain electrode of the power amplifier is improved.

The application provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. A first gate field plate electrically connected with a gate metal is added between a source field plate and a drain metal, and the first gate field plate is electrically connected with the gate metal through a resistor. In this way, the first gate field plate has a lower potential. On one hand, the first gate field plate can shield the electric field between the drain and the gate, and can further deplete the two-dimensional electron gas at the channel, so as to reduce the Cgd of the device, improve the gain and stability of the device, and avoid self-excitation of the device. On the other hand, the first gate field plate can shield the electric field between the drain and the source, reduce the Cds of the device, and thus improve the drain efficiency of the device.

The invention relates to a design method of a broadband asymmetric quasi-balanced DPA for expanding a rollback range. The design method comprises the following steps: establishing a framework of the broadband asymmetric quasi-balanced DPA, establishing an equivalent circuit model of the broadband asymmetric quasi-balanced DPA, and obtaining a mathematical relationship between voltage and current; a linear current model is adopted as an excitation signal, and load impedance, output power and drain efficiency under different normalized input levels are determined; setting the load impedance of the main power amplifier and the auxiliary power amplifier to be equal when the output power is saturated, and obtaining an adjustable proportionality coefficient of a loaded load; setting the voltage of the main power amplifier to be equal after being saturated, and obtaining a relation between a current ratio of the auxiliary power amplifier and the main power amplifier and a normalized input turn-on level; obtaining the relation between the output power back-off ratio and the normalized input turn-on level; and optimizing the isolation port load of the output coupler and the direct current bias combination of the main power amplifier and the auxiliary power amplifier at the target working frequency band so as to meet the efficiency requirement under the set output power rollback ratio.