Medium frequency signal processing method and circuit in receiver

Abstract

This invention relates to an IF signal process method and a circuit in a basic unit of a radio system receiving set defined by software among which, the circuit includes an equilizer E, multiple single channel process circuits and a combiner. The method includes a multichannel parallel process circuit used in single mode and multimode signal process, the signal channel process circuit includes an analog / digit converter ADC, digit down conversion process circuit DDC and resample interpolation circuit RS. The resample method is to resample DB to get the second sample signal of the IF analog signal DO which frequency is higher than that of DB, expanding rate and bandwidth of base band signals output.

Description

technical field [0001] The present invention relates to radio technology, communication technology, microelectronics and software technology, in particular, to the field of radio frequency and intermediate frequency signal processing of wireless communication, and more specifically, to a software-defined intermediate frequency in the basic unit of the radio system receiver Signal processing methods and circuits. Background technique [0002] A traditional radio refers to a radio whose communication function is realized by hardware. The evolution of radio technology has successively emerged analog radio, digital radio and programmable digital radio. Digital radio and programmable digital radio mainly rely on hardware to realize their communication functions. The development of hardware such as DSP, FPGA and general-purpose processor (GP) and the introduction of the concept of PC bus have led to a major change in the radio structure, and the combination of radio technology an...

AI Technical Summary

Problems solved by technology

[0007] Due to the limitation of semiconductor integrated circuit technology, the operating clock rate and input / output rate of ADC and DDC are limited, and the rate of DDC's down-order processing of digital signals is also limited, resulting in a limited maximum digital signal output rate of single-channel DDC. , the bandwidth of the baseband digital signal IF output after DDC processing is also limited, thus limiting the bandwidth of the baseband digital signal IF after DDC processing, this bandwidth can only meet the requirements of the usual baseband digital signal output; The speed of the analog / digital converter (ADC) and the processing speed and capability of the digital down converter (DDC) used to design wireless communication receivers are far from being able to meet the broadband high-frequency signals of receivers in wireless communication equipment. processing requirements, especially in applications requiring wideband digital signal output with high sampling rate

Therefore, the current implementation method of the receiver in the SDR broadband programmable and configurable radio frequency and intermediate frequency technology is problematic, and can only meet the requirements of the usual analog intermediate frequency input signal processing and the usual baseband signal output

On the other hand, the IF signal processing circuits and systems of receivers in traditional wireless communication equipment are usually designed for specific wireless communication systems, have fixed frequency sources and clock sources, and cannot be changed, so they can only be Application in systems with specific modes, specific carrier frequencies, and specific bandwidths

Images