Field effect transistors and manufacturing method thereof

Abstract

A method for forming a field effect transistor (FET) device, including forming a gate conductor and a gate dielectric on an active device region of a semiconductor wafer, the semiconductor wafer including a buried insulating layer formed on a bulk substrate and a buried insulating layer formed on a bulk substrate. A semiconductor-on-insulator layer is initially formed on the insulating layer. Source and drain extensions are formed in the semiconductor-on-insulator layer on opposite sides adjacent the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers are removed to expose a portion of the buried insulating layer. The exposed portions of the buried insulating layer are removed to expose a portion of the bulk substrate. A semiconductor layer is epitaxially grown over the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.

Description

technical field [0001] The present invention relates generally to semiconductor device processing technology, and more particularly to structures and methods for reducing Miller capacitance in field effect transistors (FETs). Background technique [0002] In the manufacture of semiconductor devices, it is an eternal driving force to increase the operating speed of certain integrated circuit devices, such as microprocessors, memory devices and the like. This impetus is provided by consumer demands for computers and other electronic devices operating at ever increasing speeds. As a result of the demand for increased speed, the dimensions of semiconductor devices such as transistors continue to shrink. For example, in devices such as field effect transistors (FETs), device parameters such as channel length, junction depth, and gate dielectric thickness are all decreasing. [0003] In general, the smaller the channel length of a FET, the faster the transistor will operate. In...

AI Technical Summary

Problems solved by technology

Another type of fringing effect that can adversely affect transistor performance is the well-known Miller capacitance

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