Method for forming memory cell and peripherial circuit

Abstract

This invention relates to one method to form memory cell and its surround circuit, which comprises the following steps: providing one baseboard with surround circuit and memory area; then forming underlay layer and cover layer on baseboard to define several channel areas and main area into surround circuit; then forming oxidation layer in main area and planting mixture into channel and then forming memory isolation layer with mixture into diffusion area; removing cover layer and under layer and forming memory materials and element wires on baseboard.

Description

technical field [0001] The present invention relates to a method for forming a semiconductor device, and in particular to a method for forming a memory unit and simultaneously forming the memory unit and peripheral circuits. Background technique [0002] The memory element is one of the important elements in the semiconductor, which is used to store electronic data. Generally speaking, a storage element that can store electronic data without peripheral power supply is called a non-volatile memory (Non-Volatile Memory) element. [0003] Currently common non-volatile memories include Erasable Programmable ROMs (EPROMs), Electrically Erasable Programmable ROMs (EEPROMs) and Flash (Flash ) memory. These memories can all be operated by the field emission mechanism (Field Emission mechanism) of channel hot electron (Channel Hot Electron, CHE) injection or Fowler-Nordheim (F-N) tunneling. [0004] Taking the flash memory element as an example, it includes a stacked gate structur...

AI Technical Summary

Problems solved by technology

However, when forming the buried drain oxide layer 140, because the thickness difference between the oxide layers 112, 116 and the nitride layer 114 of the ONO layer 100 is not large, the thickness ratio of the two is approximately equal to 1, so the buried drain oxide layer 140 is formed. The length of the bird's beak 142 of the drain oxide layer 140 cannot be reduced, which hinders the development of component miniaturization

[0012] 2. When the buried drain oxide layer 140 is formed, the buried drain oxide layer 140 will bulge upward substantially, thus causing the bottom oxide layer 112 of the ONO layer 110 to be damaged by stress

[0013] 3. Implanting impurities 130 in the substrate 100 between the channel regions 120 (such as Figure 1B As shown), if pocket implantation is to be performed, other impurities must be implanted into the substrate 100 using an inclined ion implantation process, which will cause damage to the silicon nitride layer 114 of the formed ONO layer 110

[0014] 4. After forming the buried drain oxide layer 140, because the ONO layer 110 is lifted upward, the nitride layer 114 of the ONO layer 110 may be exposed and contact with the formed word line 160 to conduct, so that the overall component greatly reduced reliability

Images