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Clock deviation arrangement method driven by production yield under technique parametric variation

A technology of clock deviation and process parameters, applied in the field of clock deviation arrangement driven by yield rate, can solve the problems of improving yield rate and unfavorable

Inactive Publication Date: 2007-09-19
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to reduce the total median error sum of squares, this algorithm makes the safety margin of some clock deviations close to zero, which is not conducive to improving the yield

Method used

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  • Clock deviation arrangement method driven by production yield under technique parametric variation
  • Clock deviation arrangement method driven by production yield under technique parametric variation
  • Clock deviation arrangement method driven by production yield under technique parametric variation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0071] The present invention is further illustrated below by specific examples.

[0072] Standard test circuits using ISCAS'89, which includes flip-flops and combinational circuits. Before arranging the clock skew, it is necessary to perform statistical timing analysis to obtain the probability distribution information of the maximum delay and the minimum delay between flip-flops with adjacent timings. When doing statistical timing analysis, it is assumed that the delay of each logic gate obeys a mutually independent Gaussian distribution N(μ, σ 2 ). In the experiment, μ=1ps and σ=0.15ps are selected.

[0073] circuit name

Number of triggers

clock skew approx.

bundle number

clock cycle

(ps)

Timing Yield (%)

Props

Method of the invention

α＝1.5

α＝

S344

15

74

19.40

84.86

87.50

1.633，87.72

S526

21

123

10.00

90.99

95.74

...

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PUM

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Abstract

The invention belongs to the IC technique field, particularly to a yield-driven clock skewing arrangement method, which comprises the steps of: setting up a statistic timing sequence restriction diagram according to the statistic result of static time series analysis, searching the key ring on the restriction diagram, redistributing the safety allowance, compacting the key ring into a over-point, updating the weight mean of the correspondent edge, inserting the relation between the key points and the compacted over-points in to a relation tree, repeating till only one over-point is left or the number of the edge is 0, traversing the tree, computing the true clock arrival time of all the leaf nodes for representing the trigger to obtain the clock skewing between the timing sequence adjacent trigger. The method takes into account of the uncertainty of the signal delay, thereby the yield of the chip will be improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a yield-driven clock deviation arrangement method. technical background [0002] In the design of synchronous digital integrated circuits, it is usually required that the clock signals of all flip-flops arrive at the same time, that is, zero deviation, to ensure the correct function of the sequential circuit. However, zero offset limits the highest frequency of signals that can function properly in a sequential circuit, thereby affecting the performance of the circuit. Scheduling useful clock skew is a very effective means of improving the performance of digital integrated circuits. [0003] The current advanced IC process level has entered the deep sub-micron stage, but the lithography precision has not been improved accordingly, resulting in a certain deviation between the IC process parameters and the design values. This causes the delay of the data s...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 方君陆伟成赵文庆
Owner FUDAN UNIV
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