Wafer level packaging method and its structure

Abstract

The invention is an integrated wafer packaging structure, comprising a chip, at least a passive component, an interface layer, an insulating layer, at least a connection, an internal connecting pad and a protection layer, where the chip comprises a surface connecting pad, an internal connecting pad and a circuit component, the passive component is formed on one side of the chip, the interface layer increases the bond between the passive component and the chip, the insulating layer covers part of the surface on the other side of the chip, the connection covers part of the surface of the insulating layer and the internal connecting pad and is used to connect with the internal connecting pad, and the protection layer is used to protect the chip.

Description

technical field [0001] The present invention relates to an integrated packaging process method, especially an integrated chip-level packaging process method, which can form at least one passive element in the packaging structure to effectively reduce the packaging volume and system volume and reduce the external contact with the passive element. Signal attenuation and failure problems caused by connections. Background technique [0002] The packaging methods of integrated circuits have been developed for a long time, and can be roughly divided into two types: pin insertion and surface mount. The surface mount method completes the electrical connection with the substrate through the metal pad. [0003] In the development process of the surface mount method, with the increasing degree of integration of the substrate circuit, many packaging methods have been developed, such as chip-scale packaging (chipscale package, CSP) with a ratio of bare die to package body area of ​​less...

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Problems solved by technology

[0005] On the other hand, in order to reduce the size of the electronic system, reduce the signal loss and noise caused by the connection of the components in the circuit board through the external wire connection, and reduce the failure probability caused by the bad connection wires, a semiconductor manufacturing process has also been developed. In this way, the integrated process of integrating passive components in the semiconductor packaging structure, but it often needs to add additional processes to form passive components, not only the process is complicated, but also the failure of the packaging structure is increased.

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