As shown in Figure 1, the clock synchronization device is a schematic diagram of the structure. The clock synchronization device is composed of a digital phase discrimination filter, a GPS receiver, a CPU, and a constant temperature high-stability crystal. The digital phase discrimination filter is connected to the GPS receiver, and the digital phase discrimination filter is connected to the GPS receiver. The phase detector filter is connected with the CPU and the constant temperature high stability crystal to form a loop. CPU: Rabbit2000, the performance is approximately equivalent to the 8051 series with 16M crystal oscillator.
 As shown in Figure 2, it is a schematic block diagram of the structure of the digital phase discrimination filter. The present invention aims at the 1pps second pulse signal (or equivalent 1pps signal) provided by this low-cost GPS receiving module as an external reference comparison signal source , Utilize the output equivalent 1pps signal of the local voltage-controlled quartz crystal oscillator controlled by the phase-locked loop of digital-analog mixing as the local comparison signal source, through the use of FPGA for digital phase discrimination and filtering technology, the output signal can be flexibly adjusted Features and accuracy to meet various needs. In the present invention, two local high-frequency signal sources are used, 1), a controllable local standard high-frequency clock source composed of a 16.384MHZ voltage-controlled crystal oscillator, through frequency division, can generate 2.048MHZ output clock and local 1pps signal. 2) The 4 times frequency of 16.384MHZ and 65.536MHZ signal are used as digital phase discrimination and filtering working clock. The digital phase detector compares the phase difference between the local second pulse signal and the external reference second pulse signal, and then through digital filtering and algorithm analysis of external supporting software, it can solve the 1pps output disturbance problem of the GPS module to ensure the accuracy of the local output signal. This can produce a variety of signal outputs equivalent to the accuracy of the input signal source.
 A digital phase discrimination filter provided by an embodiment of the present invention, and a GPS module, a 2M frequency signal source module, a CPU, and a 16.384MHZ voltage-controlled frequency unit connected to the digital phase discrimination filter respectively;
 Since digital phase detection, digital filtering and some auxiliary units are all implemented in an FPGA (programmable logic device), here is a detailed description of the design and implementation inside the FPGA.
 As shown in Figure 3, the top electrical principle inside the digital phase discrimination filter is as follows:
 The top layer includes 3 modules (module 1 to module 3), the left pin of each module is input, and the right is output. But the pin marked "bidirectional data bus" is input and output bidirectional.
 1) Interface module 1: "IO_INTERFACE", responsible for data exchange with the external CPU, receiving configuration instructions, reporting the relative phase relationship between the local second signal and the external reference second signal, etc.; the input of interface module 1 is connected to the GPS module and 2M frequency respectively The signal source module is connected to the CPU via the data bus; according to the configuration, an external reference source is selected and converted to the second pulse output EXT_1PPS as the external reference basis for phase discrimination. For example, through the address line ADDRES[31..24], /CS, ALE, /WR, the CPU writes the content on the data line DB[7..0] corresponding to the address x"00" into this module, If the data content is x "00", it indicates that "GPS_1PPS" is selected as the external reference source, and the interface module can directly output it to the module output port "SEL_1PPS" for external modules; if the data content is x "01", then Indicates that the first channel (2MHZ) in "2MHZ[4..1]" is selected as the external reference source. Since the frequency input is 2.048MHZ at this time, the module divides the frequency to generate 1pps second pulse , And output it to the module output port "SEL_1PPS" for external module use; other analogy, so that the "external reference" second pulse is generated.
 In the same way, the CPU also writes the duty cycle parameters of the output signal and the filter parameters into the module, and outputs them to the ports of the interface module "PW[7..0]" and "FILT_D[7..0]" respectively for External modules are used.
 In addition, the "UP", "DOWN", and "OVER_DIR" phase comparison output signals from the external module are also provided by this interface module to the CPU to access and read in the same way.
 In this way, the CPU can uninterruptedly grasp the relative phase relationship between the external reference source and the local source through the data line, so as to adjust the controllable local standard high-frequency seed source composed of the voltage-controlled crystal oscillator, so that it continues to be repeated , Through the specific algorithm of the CPU, the stable state of the closed-loop feedback loop is finally reached, and the local output signal is precisely kept track of the external reference source.
 2) Local module (LOCAL_CQ)2, used to complete the frequency division of the input frequency of the local crystal oscillator, divide the frequency according to the frequency division coefficient from 16.384MHZ to 1hz, and extract other required frequencies, and also according to the CPU configuration The pulse width data adjusts the duty cycle of the output second pulse; the input terminals of the local module 2 are respectively connected to the external reference second pulse output terminal of the interface module 1, the filter parameter output terminal, the reset bit output terminal and the 16.384MHZ frequency signal source module , The local module 2 is equipped with other required frequency output terminals such as second pulse, 2.048MHZ, 200HZ, 8KMHZ and other signals; in addition, after receiving the re-synchronization setting instruction of the CPU, the status of the divider should be compared with the external reference The phase of the second signal is aligned again. The generated second pulse L1PPS is the local reference basis for phase discrimination.
 The core here is a synchronous clock fixed modulus counter that can be set asynchronously, with a modulus value of 16.384×10 6 , Whenever the count value returns to zero, it is the starting edge of the local second pulse, and the width of the high level is determined by the value of the "PW_D[7..0]" port. When the counter value is less than or equal to PW_D[7. .0], the output remains high, otherwise it is low. If you want to expand the adjustment range, you can increase the number of bits in the pulse configuration data "PW_D[7..0]" to achieve, thus, "local" The second pulse is generated. In addition, when the RESYN terminal receives the reset bit signal, it generates a narrow pulse and ensures that it is synchronized with the rising edge of the second pulse of the external reference. The counter is asynchronously cleared by this narrow pulse, so that after the reset bit , The state of the local counter is consistent with the external reference source. The purpose of this processing is to speed up the tracking and locking process of the external reference source, and it can also simplify the digital phase discrimination and filter circuit of subsequent modules, because after resetting the bit , The phase of the local second pulse is almost the same as that of the external reference source. In a short period of time, the phase difference between the two will not drift too much, so the observation range of the filter circuit can be reduced.
 3) Data processing module (DP_CTRL) 3, used for phase detection between the internal and external pulses, and also includes an adjustable digital filter. The input terminals of the data processing module 3 are respectively connected to the output terminal of the interface module 1, the output terminal of the local module 2 and the 4 times frequency output terminal of the 16.384MHZ frequency signal source module, and the output terminal of the data processing module 3 connects to the input terminal of the interface module 1. ;
 The phase detection of this data processing module is to detect the relative phase relationship between two pulses. These two input pulses are the "external reference" second pulses and the "local" second pulses that have been processed by the external module described previously. The phase result can reflect the relative position and change trend between the "external reference" second pulse and the "local" second pulse. The phase discrimination result is updated every second.
 The introduction of the adjustable digital filter, on the one hand, can shield the occasional circuit interference. The main function is that when the "external reference" second pulse is generated by the GPS receiving module, its inherent second pulse "disturbance" is relatively Larger, as measured by a high-precision clock system, its phase jump does not meet the requirements, and it will also interfere with the phase detection result of the phase detector, especially when the local clock source has actually been compared with the external reference This phenomenon will be more obvious when the sources are highly consistent. For this reason, the role of the filter here is to filter out this kind of phase "jumping" as much as possible, or in other words, to remove the "burst" "large phase difference" Reported to the CPU, the CPU will determine the current actual state according to a certain algorithm, so as to avoid unnecessary adjustments or "over-adjustment" caused by the output signal performance index decline. However, a practical use problem needs to be considered because of the potential differences between individual circuit components, especially the possible differences in the electrical performance of the GPS receiving module (for example: different manufacturers, different production batches, etc. ), it is possible to lose the effectiveness of the filter using fixed parameters. For this reason, the filter parameters here are settable and controlled by the CPU in real time. Therefore, the phase difference width of the "filter" can be used. The changes have greatly improved the reliability and practicability of circuit performance.
 In addition, because "speed" and "precision" have always been a pair of contradictions, the filter range becomes smaller and the system tracking accuracy becomes higher, but it takes longer for the system to enter a stable state. On the contrary, the filter range becomes larger and the system tracking accuracy becomes lower. , But the system enters the stable state faster. For this reason, for different applications, appropriately adjusting the parameter settings of the filter can change the overall response speed of the system and improve work efficiency.
 As shown in Figure 4, it is the electrical schematic diagram in the "DP_CTRL" module. The data processing module is provided with a phase detector unit 4 and filter units 5 and 6;
 Phase detector unit (V_DPD) 4: It is a digital phase detector constructed with VHDL hardware description language. The input terminal of phase detector unit 4 is respectively connected to the external reference second pulse output terminal of interface module 1 and the local reference second of local module 2. The pulse output terminal is used to identify the phase relationship between the two input pulses. The edge of the pulse is used to identify it. It is independent of the input pulse width and has a high resolution. When the input local second signal frequency is higher or the phase is advanced When referring to the second signal, the output "DOWNDIR" will change to '1', otherwise "UPDIR" will change to '1'. When both are ‘0’, it means that the two input pulses are exactly the same, that is, the same frequency and the same phase. When "DOWNDIR" is ‘1’, it indicates that the frequency of the local voltage-controlled crystal oscillator is to be lowered, and when "UPDIR" is ‘1’, it means that the frequency of the local voltage-controlled crystal oscillator is to be increased and accelerated. The frequency addition and frequency reduction indication output terminals of the phase detector unit 4 are respectively connected to the frequency addition control and frequency reduction control input terminals of the interface module 1 via an AND gate.
 a) Lead filter unit (V_OVER_CTRL) 5, lag filter unit (V_OVER_CTRL) 6, are digital filters constructed with VHDL hardware description language for overflow indication; when the difference between the two input pulses exceeds FID[7..0 ] When the value is set, "OVER_ACT" outputs '1' level. Two such modules are used here to distinguish two relative states: a. The local second signal overflows ahead of the external reference second signal, b. The local second signal lags behind the reference second signal overflow, and merges into one "OVER_DIR" output for CPU detection. FID[7..0] is set by the CPU and can be dynamically adjusted. It reflects "clk×4" "The number of cycles of the input clock (ie 65.536MHZ), changing its value, can change the characteristic parameters of the output clock.
The input ends of the lead filter unit 5 are respectively connected to the frequency addition indication output end of the phase detector unit 4, the 4 times frequency output end of the 16.384MHZ frequency signal source module, the filter parameter output end of the interface module 1, and the lag filter unit 6 The input terminals are respectively connected to the frequency reduction indicator output terminal of the phase detector unit 4, the 4 times frequency output terminal of the 16.384MHZ frequency signal source module, the filter parameter output terminal of the interface module 1, the lead filter unit 5 and the lag filter unit The overflow indication output terminal of 6 is connected to the overflow control input terminal of interface module 1 via the OR gate.
 Mathematical regression is used to estimate the two kinds of errors, so as to separate the respective errors, and correct the cumulative errors of the crystal, thereby constructing a simple and high-precision clock generating device. Specifically, the output clock of the high-precision clock is divided by the frequency division circuit, and the second pulse signal obtained after frequency division is compared with the second pulse signal of the GPS through the digital phase detector filter to obtain the phase deviation sequence sample and the cumulative error of the crystal oscillator. The compensation value is set by the CPU to correct. It is adjusted once every second, and the compensation value at the Nth second is estimated from the historical data of the GPS clock error of the previous N-1 second and the compensation value of the previous N-1 second using the linear regression algorithm to obtain the estimated compensation value. The algorithm is as follows:
 Step 1. Establish a mathematical model of GPS clock synchronization crystal oscillator clock
 There is a certain error e between the GPS output clock and the international standard time, and e obeys the normal distribution:
 ε~N(0,σ 2 ). (1)
 s time series X:
 1, 2, 3, 4,...,x,...,n (2)
 The international standard time corresponding to the s clock sequence output by GPS can be recorded as
 1-e 1 , 2-e 2 , 3-e 3 , 4-e 4 ,..., x-e x ,..., n-e n (3)
 The general formula is expressed as y x ′=x-ε x x∈N ε x ~(0,σ 2 ) (4)
 Where y x ′ Is the international standard time corresponding to the xth clock of the GPS output, and the time error is e x.
 Suppose the initial deviation between the 0th s clock of the s clock sequence generated by the crystal oscillator frequency division and the international standard time is a; the time interval error is b; because the random error of the high-precision crystal oscillator is much smaller than the random error of the GPS s clock (for example, the accuracy is 10 -9 The random error of the crystal oscillator of s<1ns), so regardless of the random error of the crystal oscillator s clock, the clock sequence generated by the crystal oscillator frequency division output s clock can be recorded as the international standard time
 1+a+b, 2+a+2b, 3+a+3b, 4+a+4b,..., x+a+bx,..., n+a+bn (5)
 The general formula is expressed as y x "=x+a+bx x∈N (6)
 Where y x "Is the international standard time corresponding to the x-th s clock output by the frequency division of the crystal oscillator, and the time error is
 m(x)=a+bc (7)
 Then the deviation of the crystal oscillator frequency division s clock (referred to as the crystal oscillator s clock) and the GPS s clock is
 y x =y x ″-Y x ′=a+bx+ε x x∈N (8)
 The deviation sequence Y can be expressed as
 y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 ,..., y x ,..., y n (9)
 From the time series of Y, a and b can be estimated to calculate the clock error m(x) of the crystal oscillator s; at the same time, the time series of Y can calculate the error e of the GPS x Estimation can be used to measure the accuracy level of the GPS receiver.
 Step 2. Error estimation of crystal oscillator s clock
 Using the unary linear regression model of formula (8), that is, using the regression equation of formula (7) to analyze the correlation characteristics of the time series X and the deviation series Y, carry out the least square estimation of a and b, and the estimated values are respectively
 b ^ = Σ x = 1 n ( x - x ‾ ) ( y x - y ‾ ) Σ x = 1 n ( x - x ‾ ) 2 - - - ( 10 )
 a ^ = y ‾ - b ^ x ‾ - - - ( 11 )
 Where y and x are the average values of the deviation series Y and the time series X respectively,
 x ‾ = 1 n Σ x = 1 n x = n + 1 2 - - - ( 12 )
 y ‾ = 1 n Σ x = 1 n y x - - - ( 13 )
 Then the estimated error between the xth s clock output by the crystal oscillator and the international standard time for
 μ ^ ( x ) = a ^ + b ^ x - - - ( 14 )
 owned It is a time quantity, the unit is second, and it needs to be converted with the control quantity voltage of the high stability crystal (unit is V). The control voltage is determined by the control amount of the D/A chip, and the conversion formula is as follows:
 ΔDA = μ ^ ( x ) * D MAX f Max f MIN - 1 - - - ( 15 )
 Where D MAX Depends on the number of bits of the DA conversion chip, if DA is a sixteen-bit conversion chip, then D MAX = 65536. If DA is an eight-bit conversion chip, then D MAX =256. f MIN Is the minimum frequency adjusted to the voltage-controlled high-stability crystal, f MAX It is the maximum frequency that the voltage-controlled high-stability crystal can be adjusted to.
 According to the error estimate The obtained ΔDA adjusts the crystal oscillator s clock to produce a high-precision clock output.
 Step 3. Estimation of s clock error output by GPS receiver
 The estimation of the second pulse error output by the GPS receiver is actually an estimate of σ in equation (1) 2 Estimation, due to σ 2 =D(ε)=E(ε 2 ) Is the second-order origin distance of e. According to the distance estimation method, the second-order origin distance of the sample can be used as its estimated value
 σ ^ 2 = 1 n Σ x = 1 n ϵ x 2 - - - ( 16 )
 And from equation (8), we have
 ε x =y x -a-bx (17)
 use Replacing a and b respectively, we get σ 2 Estimator
 σ ^ 2 = 1 n Σ x = 1 n ( y x - a ^ - b ^ x ) 2 - - - ( 18 )
 The size reflects the accuracy of the receiver's output per second pulse. When the error estimate When the GPS receiver is out of synchronization or malfunction.
 As shown in Figure 5, it is a block diagram of the GPS clock adjustment algorithm flow diagram of the least squares model. The present invention divides the output clock of the high-precision clock through the frequency divider circuit, and the second pulse signal is obtained after the frequency division and passes through the digital phase detector filter and The GPS second pulse signal is phase-compared to obtain the phase deviation sequence sample, and the cumulative error of the crystal oscillator is corrected by the compensation value set by the CPU. It is adjusted once every second, and the compensation value at the Nth second is estimated from the historical data of the GPS clock error of the previous N-1 second and the compensation value of the previous N-1 second using the linear regression algorithm to obtain the estimated compensation value. Use this compensation value as a correction to adjust the frequency of the high-stability crystal, and calculate the compensation value for the next second from the current phase discrimination result. The steps are as follows:
 The first step: Calculate the control initial value DA of the D/A converter chip according to the parameters of the voltage control crystal, and power on the control crystal with this initial value. The specific method is as follows:
 In this example, the frequency adjustment range of the high voltage regulator control crystal is 16.384M±15Hz, the DA conversion chip is 16 bits, the reference voltage is 5V, the output voltage is 0 when the DA value is 0, and the output frequency is 16.384M-15Hz. When DA is assigned as 0, the output voltage is 5V, and the output frequency is 16.384M+15Hz. In order to ensure that the initial value of the power-on frequency is approximately 16.384M, the value of DA is 32768;
 Step 2: Align the second pulse of the crystal with the second pulse of GPS and start tracking;
 The third step: adjust the crystal according to the phase difference calculation corresponding to the crystal voltage adjustment value, the phase lags to speed up the frequency, the phase leads to reduce the frequency, and the process of fast tracking GPS begins. The purpose of this process is to make the center value of the crystal's output frequency enter a more accurate range and fluctuate slightly within this range. This process lasts for half an hour, and the last four hundred phase difference data (that is, the deviation sequence Y of Equation 9) is recorded. At this time, the crystal control voltage D/A value is DA, and DA is 32210 in this example. Record the value of s time series X (formula 2) as four hundred;
 Step 4: Every second, the phase difference of the first X-1 second is estimated by the linear regression algorithm to estimate the phase difference of this second (Suppose this example is +5ns) (see formula 14), according to the corresponding relationship between phase and frequency and the calculation relationship between high-stability crystal frequency and control voltage, calculate the compensation value of the crystal control voltage value ΔDA1 = -179 (see formula 15). The control parameter for correcting the voltage of the crystal with this compensation value is DA+ΔDA1=32210-179=32031. After the adjustment is completed, X is incremented to 401; after the adjustment is completed, the DA value is updated to DA=DA+ΔDA1=32031;
Step 5: If the difference in this second is greater than 100ns (2σ when using MOTOROLA VP ONCORE, the probability of the accuracy of the second phase detection result (leading/lagging) is equal to 95.46% of the GPS second pulse falling within 2σ. ) If this example is +105ns, it can be considered that the phase difference is too large, and certain phase compensation must be performed. The compensated phase is the part that exceeds 100ns. The calculation is based on the corresponding relationship between phase and frequency and the calculation relationship between high-stable crystal frequency and control voltage. The compensation value of the crystal control voltage value ΔDA2 = -179 (see formula 15), and the control parameter for correcting the crystal voltage with this compensation value is DA+ΔDA2=32031-179=31852; the DA value will not be updated after the adjustment is completed;
 Step 6: Repeat the fourth step and repeat the correction. The longer the time, the more the number of samples. At this time, the voltage control parameter DA of the voltage control crystal will fluctuate slightly along a certain central value, and the overall approach will be one. Horizontal straight line. The linear regression overcomes the influence of the second pulse jitter.