Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor structure and its making method

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as delamination of protective layer 106, component damage, and component reliability reduction, so as to avoid reliable The effect of reducing

Inactive Publication Date: 2008-01-09
UNITED MICROELECTRONICS CORP
View PDF0 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the wafer is covered with a variety of different material layers, during the wafer dicing operation, the material layers on the dicing road will have different material properties from each other, which will cause cracks or delamination on the dicing road. The delamination phenomenon often causes external moisture to enter the chip through the delamination, resulting in reduced reliability of components or damage to components on the chip.
[0007] For example, when the diamond cutter cuts along the dicing line of the wafer, the test pad 104 is affected by the stress and presses the protective layer 106, so that the protective layer 106 is delaminated, and then the protective ring (die sealring) located at the periphery of the chip is delaminated. ) is damaged, and external moisture will enter the chip through the interface between the protective layer 106 and the dielectric layer 102, reducing the reliability of the components on the chip

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure and its making method
  • Semiconductor structure and its making method
  • Semiconductor structure and its making method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0053] 2A to 2C are cross-sectional views of a fabrication process of a semiconductor structure according to an embodiment of the present invention. First, please refer to FIG. 2A , a substrate 200 is provided. The substrate 200 has a scribe line area 201 and a device area (not shown). Then, a dielectric layer 202 is formed on the substrate 200 . The material of the dielectric layer 202 is, for example, a low dielectric constant (low-k) material. In addition, the same interconnection structure or other element structures (not shown) as those in the dielectric layer 202 in the device region have been formed in the dielectric layer 202 in the scribe area 201, and these interconnection structures or other The component structure acts as the test key. Next, a test pad 204 is formed on the dielectric layer 202 of the scribe line area 201, and the test pad 204 is electrically connected to the above-mentioned interconnect structure or other component structures, so that testers ca...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention is concerned with the semiconductor junction structure, which is located on the basis of the cutting path area of the wafer. It includes: the first dielectric layer, the first testing land, and the protecting layer. It is: the first dielectric layer arranges on the basis; the first testing land arranges on the first dielectric layer; the protecting layer arranges on the first dielectric layer that is located around the first testing land; between both sides of the protecting layer and the first testing land is the groove that is at least located between the first testing land and the cutting path area.

Description

technical field [0001] The invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a semiconductor structure and a manufacturing method thereof which prevent film layers on a cutting line from being delaminated during wafer cutting. Background technique [0002] With the advancement of technology, semiconductor manufacturing has become one of the most important industries. However, in order to meet different needs, the manufacturing process of semiconductors has become more and more complicated. Therefore, it is necessary to manufacture high-yield and low-cost Chips are becoming more and more difficult. [0003] In order to obtain information on the pros and cons of the process at any time during the semiconductor chip manufacturing process, a special design will be made on the periphery of the semiconductor chip (chip), that is, on the wafer with multiple parallel and perpendicular scribe lines. A plurality of test keys, and thes...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/00H01L21/00
Inventor 饶瑞孟郭建利陈慧玲陈宝娟
Owner UNITED MICROELECTRONICS CORP