Non-pin packaging structure of semiconductor element and packaging technology thereof
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A packaging structure and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. Eliminate problems such as falling off, achieve the effects of saving development costs, improving reliability, and enhancing binding force
Active Publication Date: 2008-02-27
JCET GROUP CO LTD
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[0005] 2. The chip carrying base is easy to fall off, which will lead to product failure-the bonding surface between this whole and large metal structure and the plastic encapsulation compound is limited, so the structural strength is low; when the product is repeatedly mounted on the surface, the whole The chip carrying base of the block is easily pulled out of the plastic package due to force, causing the chip
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[0050] Process example 1: Engraving first and then plating
[0051] The encapsulation process of the semiconductor device of the present invention without feet encapsulation comprises the following steps:
[0052] ——Take a piece of metal substrate 9, as shown in Figure 3;
[0053] ——Affix a mask 10 on the front and back sides of the metal substrate 9 to protect the subsequent etching process, as shown in Figure 4;
[0054] ——Removing part of the mask 10 on the front of the metal substrate 9, the intention is to expose the area on the metal substrate to be half-etched, as shown in Figure 5;
[0055] - Half-etching the area where the mask was removed in the previous process, forming a recessed half-etching area 9.1 on the front surface of the metal substrate 9, and at the same time forming a relatively preliminary bump-shaped wiring pin carrying base 2 and a plurality of chip carrying bases An independent metal bump 1.1, as shown in Figure 6;
[0056] ——Remove the remaining mas...
Example Embodiment
[0072] Process Example 2: Engraving after Plating
[0073] The engraving and engraving engraving process after the first plating of the semiconductor device of the present invention includes the following steps:
[0074] ——Take a piece of metal substrate 9, as shown in Figure 3;
[0075] ——Affix a mask 10 on the front and back sides of the metal substrate 9 to protect the subsequent etching process, as shown in Figure 4;
[0076] ——Remove part of the mask 10 on the front of the metal substrate 9 to expose the area on the metal substrate to be plated with a metal layer, as shown in Figure 5-1;
[0077] ——Carry out the metallization operation on the area where the mask was removed in the previous process, and form metal layer II7 and metal layer III8 on the front of the metal substrate 9, as shown in Figure 6-1;
[0078] ——Remove the remaining mask 10 on the front of the metal substrate and the mask 10 on the back of the metal substrate, as shown in Figure 7-1;
[0079] - Cov...
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Abstract
The present invention relates to a semiconductor non-pin-packaging structure and its packaging process. The said structure includes chip substrate (1), wire-bonded pins substrate (2), chip (3), metal wire (4) and plastic package (5). Bottoms of the said chip substrate (1) and wire-bonded pins substrate (2) protrude bottom of the plastic package (5). The chip substrate is consisted of two parts, of which one is set in the plastic package, and the other is set outside the plastic package. The part in plastic package is consisted of several independent metal protrusions (1.1) which extend to outside of the plastic package, and all connect onto a complete metal sheet (1.2). The outer metal sheet (1.2) shows a pallet pattern to support the several independent metal protrusions (1.1) in the plastic package, and protrudes from the bottom of the plastic package (5), thus it consists another part of the chip substrate; the said chip is set on the metal protrusions of chip substrate. The present invention will not lead to layered and unattaching of the chip substrate, can be applied in high power, high heat-distributed productions.
Description
technical field [0001] The invention relates to a footless packaging structure of a semiconductor device and a packaging process thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] The traditional semiconductor device chip carrier base exposed footless package structure uses a whole piece / a whole piece of metal as the chip carrier base (as shown in Figure 1) [0003] This chip carrying base structure has the following disadvantages: [0004] 1. A large amount of stress residue is likely to be generated in the packaged product, which will affect the reliability of the product. The materials in the package can be divided into three categories: metal (copper, iron, nickel, etc.), chip (silicon material) and plastic packaging compound. From the perspective of the thermal expansion coefficient of the material, the thermal expansion rate of the chip and the plastic packaging compound is similar, while the thermal expansion rate of t...
Claims
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