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Method for optimizing probe station pricking times

A technology of probe station and number of times, which is applied in the direction of electronic circuit testing, measuring devices, instruments, etc., can solve the problems of wasting wafer testing time, unable to optimize the number of needles, redundant needles, etc., to save a lot of test time, The effect of reducing test cost and shortening test time

Inactive Publication Date: 2010-09-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitation of the design of the existing probe station, the number of needle sticks cannot be optimized by itself, so there may be some redundant needle stick times, which wastes the testing time of the entire wafer

Method used

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  • Method for optimizing probe station pricking times
  • Method for optimizing probe station pricking times
  • Method for optimizing probe station pricking times

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Experimental program
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Embodiment Construction

[0010] like image 3 As shown, adopt the method of the present invention to carry out mass production parallel test to multi-chip wafer, can adopt the hardware testing system 1 that is made of hardware such as large-scale logic tester, automatic probe station and special-purpose probe card, will be made up of operating system, A software testing system 2 composed of a dedicated test program and a dedicated test vector is input into the hardware system 1 for testing.

[0011] The test object is a mass-produced chip (device under test). The number of parallel tests is determined by the way the tester can support, which can be 4 / 8, 16 / 32, etc.

[0012] The shape of the test probe card is rectangular: such as AxB, A and B can be 1, 2, 4, 8, 16. The same measurement methods are: 1x(2 / 4 / 6 / 8 / 16), 2x(2 / 4 / 6 / 8 / 16), 4x(2 / 4 / 6 / 8 / 16), 8x(2 / 4 / 6 / 8 / 16) or 16x(2 / 4 / 6 / 8 / 16).

[0013] The special test program of the software test system 2 adopts the method of calculating all possible stepping...

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Abstract

This invention discloses a kind of method to optimize the puncture time of the probe station, calculates all of the possible puncture line and time by collecting the data of all slug location in the crystal circle, and according to the probe card shape and its match shape to the crystal circle, gets the least puncture time according to the result. The method in this invention can reduce the test time of the whole crystal circle in maximum limits; it reduces the test cost hugely, advantages the competition of the slug.

Description

technical field [0001] The invention relates to a method for optimizing test time in the mass production test of a large-scale integrated circuit chip, in particular to a method for optimizing the number of needle sticks on a probe station. Background technique [0002] In the mass production test of large-scale integrated circuit chips, the test time is a very important indicator, and the number of needle sticks and test time are different for each wafer. Due to the limitation of the design of the existing probe station, it is impossible to optimize the number of needle sticks by itself, so there may be some redundant needle stick times, which wastes the testing time of the entire wafer. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for optimizing the number of times of needle sticking of the probe station, which can maximize the optimization of the number of needle sticking of the probe station, ther...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/00G01R31/26G01R31/28H01L21/66
Inventor 杜发魁桑浚之惠力荪
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP