Method for optimizing probe station pricking times
A technology of probe station and number of times, which is applied in the direction of electronic circuit testing, measuring devices, instruments, etc., can solve the problems of wasting wafer testing time, unable to optimize the number of needles, redundant needles, etc., to save a lot of test time, The effect of reducing test cost and shortening test time
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[0010] like image 3 As shown, adopt the method of the present invention to carry out mass production parallel test to multi-chip wafer, can adopt the hardware testing system 1 that is made of hardware such as large-scale logic tester, automatic probe station and special-purpose probe card, will be made up of operating system, A software testing system 2 composed of a dedicated test program and a dedicated test vector is input into the hardware system 1 for testing.
[0011] The test object is a mass-produced chip (device under test). The number of parallel tests is determined by the way the tester can support, which can be 4 / 8, 16 / 32, etc.
[0012] The shape of the test probe card is rectangular: such as AxB, A and B can be 1, 2, 4, 8, 16. The same measurement methods are: 1x(2 / 4 / 6 / 8 / 16), 2x(2 / 4 / 6 / 8 / 16), 4x(2 / 4 / 6 / 8 / 16), 8x(2 / 4 / 6 / 8 / 16) or 16x(2 / 4 / 6 / 8 / 16).
[0013] The special test program of the software test system 2 adopts the method of calculating all possible stepping...
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