Chip embedding bury type packaging structure

Abstract

A chip-embedded encapsulation structure is provided, which consists essentially of a bearing board with a raised section, a semiconductor chip formed on the raised section of the bearing board, an insulation layer formed on the bearing board and the semiconductor chip, as well as a circuit layer formed on the insulated layer. The circuit layer can be electrically connected to an electrode cushionof the semiconductor chip through a plurality of conductive structures so that the semiconductor chip can electrically extend outwards. By adjusting the thicknesses of the raised section of the bearing board, the insulation layer and the bearing board, warping phenomenon of the encapsulation structure caused by changes of temperature during manufacture can be controlled.

Description

technical field [0001] The invention relates to a chip-embedded package structure, in particular to a package structure which embeds a semiconductor chip and makes it electrically extended outward. Background technique [0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. Traditional semiconductor devices mainly install a semiconductor component such as an integrated circuit on a package substrate or a lead frame, and then The semiconductor component is electrically connected to the packaging substrate or the lead frame, and then packaged with glue. Among them, Ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized in that a packaging substrate is used to place semiconductor components, and self-alignment technology is used to implant semiconductor components on the back of the packaging substrate. A plurality of solder balls (Solder ball) arranged ...

AI Technical Summary

Problems solved by technology

[0007] Although the packaging structure of the chip embedded in the substrate can solve the above-mentioned defects of the prior art, however, due to the large difference in the coefficient of thermal expansion (Coefficient of Thermal Expansion, CTE) of the heat dissipation plate 12 and the insulating layer 14, the substrate structure in the manufacturing process is difficult. When the temperature changes (such as substrate baking (Baking), subsequent thermal cycle (Thermal Cycle) operations and other environments, different thermal stresses (Thermal Stress) are generated on each component), which is easy to cause the structure to warp (Warpage) phenomenon In severe cases, it may cause delamination between the structural layers, and even squeeze the semiconductor chip, causing the chip to break

However, increasing the thickness of the heat dissipation plate to balance the thermal stress on the substrate during temperature changes can effectively improve the substrate warpage phenomenon, but increasing the thickness of the heat dissipation plate will significantly increase the volume and thickness of the finished package structure, and will result in cost of the manufacturing method increase

[0008] In addition, most of the semiconductor chips embedded in the above packaging structure are of a single form and the same size, and have not yet formed a multi-functional module structure, which does not conform to the current development trend of electronic products.

In addition, if a variety of semiconductor components with different sizes are embedded in the package structure to achieve a multifunctional module structure, the electrical connection surfaces of these components are not in the same position due to the different sizes of the embedded components. The surface of the insulating layer on the surface of the packaging substrate where these components are embedded is uneven, and even affects the manufacturing quality of subsequent fine lines on the insulating layer

[0009] Therefore, how to propose a chip-embedded packaging structure to overcome the warping of the structure during the manufacturing process of the existing semiconductor packaging structure, the increase in the thickness, weight and cost of the packaging structure, the uneven manufacturing surface, the inability to improve the ability of the circuit manufacturing method, and the interface Problems such as difficult integration and inability to effectively dissipate heat have become technical problems that need to be overcome urgently in this field

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