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Shallow impurity drain domain logical operation method suitable for active region read only memory

A read-only memory and logic operation technology, applied in the field of shallow-doped drain layout logic operation, can solve problems such as errors and inability to apply active area read-only memory, and achieve the effect of small layout area

Active Publication Date: 2011-04-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The advantage of the above process is to save the layout area, but because the LDD area is related to the shape of the MOS tube channel, once the shape of the ACT changes, the LDD will also change. That is to say, if the ACT mask is changed, a new LDD must be produced Mask, so that this relatively new process cannot be applied to active area read-only memory (ACT ROM) products, because once the ACT mask is changed, but the LDD does not change, it will cause the same error as shown in Figure 6

Method used

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  • Shallow impurity drain domain logical operation method suitable for active region read only memory
  • Shallow impurity drain domain logical operation method suitable for active region read only memory
  • Shallow impurity drain domain logical operation method suitable for active region read only memory

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Embodiment approach

[0021] As shown in FIG. 7, the present invention provides a shallowly doped drain layout logic operation method suitable for active area read-only memory, comprising the following steps:

[0022] Step 1. Determine the boundary of the re-injection layer to obtain area A;

[0023] Step 2, determining the channel region of the Metal Oxide Semiconductor (MOS) transistor where the grid gate overlaps with the active region;

[0024] Step 3. Increase a on each side of the area determined in step 2 to obtain area B, where a can be adjusted according to the specific process capability. In some 0.15 micron logic processes, the range of a value can be selected to be 0.3-0.5um;

[0025] Step 4. Collect the two areas A and B respectively obtained in Step 1 and Step 3 to obtain Area C;

[0026] Step 5. In the region C determined in step 4, perform ion implantation to generate LDD.

[0027] The N-type or P-type LDD layer (NLDD / PLDDlayer) produced by the logic process provided by the presen...

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Abstract

The invention relates to a method for logically calculating shallow-doping drain layout of a read-only storage in an active region; a border of a heavy injection layer is firstly determined to obtain a region A; a groove region of metal oxide semiconductor tube overlapped by a gate and the active region is determined; each side of the region is increased by a to obtain a region B; a collection ofthe A and the B is taken to obtain a region C; lastly ion implant is carried out in the region C to generate LDD. The method for logically calculating shallow-doping drain layout of the read-only storage in the active region of the invention has the advantages that: every time when the code is changed, only ACT is needed to be changed and the LDD layer is not needed to be changed; and at the sametime a smaller layout area is maintained.

Description

technical field [0001] The invention relates to a shallow-doped drain layout logic operation method suitable for an active area read-only memory. Background technique [0002] The active area read-only memory (ACT ROM) is simple in structure, stable in storage, and highly integrated. It is a non-volatile read-only memory commonly used in logic products. Generally, the stored logic codes '0' and '1' are judged according to whether there is a channel. The heavily doped area (Plus) of the active area read-only memory (ACT ROM) covers the entire ROM logic code area, and its code change only needs to change the mask of the active area (as shown in Figure 1), which means that the same logic product will Corresponds to many active area masks, but all masks can be shared. [0003] LDD (lightly doped drain lightly doped drain) is generated through layout logic operations. Two ion implantations of LDD and Halo (also known as Pocket) are performed. Part of the LDD and most of the Ha...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8246H01L21/265H01L27/02H01L27/112G06F17/50H10B20/00
Inventor 何军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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