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HVMOS and semiconductor device integrating HVMOS and CMOS

A semiconductor and conductor technology, applied in the field of semiconductor devices, can solve the problems of long channel, increased unit area, and high energy consumption

Active Publication Date: 2008-07-23
SUZHOU XYSEMI ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the long channel of HVMOS, the parasitic capacitance is large, such HVMOS needs to consume a lot of energy to drive, and the speed of turning on and off is also very slow, so the switching frequency is very low, such as 300 kHz
On the other hand, the long channel of HVMOS makes the channel resistance large and the unit area also increases. The HVMOS with the same on-resistance design occupies a large chip area.

Method used

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  • HVMOS and semiconductor device integrating HVMOS and CMOS
  • HVMOS and semiconductor device integrating HVMOS and CMOS
  • HVMOS and semiconductor device integrating HVMOS and CMOS

Examples

Experimental program
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Effect test

Embodiment 1

[0015] A kind of HVMOS as shown in Figure 14, can be either a HVPMOS or a HVNMOS, located on a semiconductor substrate / epitaxial layer 211, each of the HVPMOS and HVNMOS includes a channel located on the surface of the substrate / epitaxial layer 211, and a gate 270 on the channel. The HVPMOS also includes: a source / drain, the source / drain includes a lightly doped region 251 next to the channel and next to the channel and a lightly doped region 251 next to the channel heavily doped region 261; another source / drain, the other source / drain includes another lightly doped region 256 next to the channel and next to the channel and a next to the other A heavily doped region 261 of a lightly doped region 256, the other lightly doped region 256 is of the same doping type as the lightly doped region 251; A heterowell 241, the oppositely doped well 241 is located below the channel and does not completely contain the channel; another oppositely doped well 235 with the opposite doping type...

Embodiment 2

[0025] As shown in Figure 14, a semiconductor device integrating HVMOS and CMOS includes a CMOS and an HVMOS disposed on a semiconductor substrate / epitaxial layer 211, and the CMOS can be either an NMOS or a PMOS, or both Both are included, the HVMOS can be either a HVNMOS or a HVPMOS, or both can be included. It is characterized in that the PMOS and the NMOS respectively include:

[0026] a channel on the surface of the substrate / epitaxial layer 211, a gate 270 on the channel,

[0027] a source / drain comprising a lightly doped region 251, 252 and heavily doped regions 261, 262 adjacent to the lightly doped region 251, 252,

[0028] A counter-doped well 241, 242 of opposite doping type to the source / drain.

[0029] It is also characterized in that the HVPMOS and the HVNMOS respectively include:

[0030] a channel on the surface of the substrate / epitaxial layer 211, a gate 270 on the channel,

[0031] A source / drain comprising a lightly doped region 251, 252 next to the cha...

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PUM

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Abstract

The invention provides an HVMOS and an integrated HVMOS and a CMOS semiconductor device. The HVMOS comprises a substrate, a channel, a gate and a source / drain, wherein the source / drain comprises a light doping area and a heavy doping area, wherein the light doping area is arranged beside the channel and is next to the channel, and the heavy doping area is next to the light doping area, another source / drain comprises another light doping area and another doping area, wherein the another light doping area is arranged beside the channel and is next to the channel, and the another heavy doping area is next to the another light doping area. A reverse doping well whose doping type is opposite to the source / drain comprises the source / drain, and another reverse doping well whose doping type is opposite to the source / drain is located between the another light doping well of the another source / drain and the reverse doping well. The HVMOS fully uses prior process of the CMOS, thereby greatly reducing the number of mask layers, and has the advantages of small conduction resistance, low parasitic capacitance, fast switch speed, high switching frequency and low cost and the like.

Description

technical field [0001] The invention relates to a high voltage metal oxide semiconductor transistor (High Voltage Metal Oxide Semiconductor, HVMOS) and a semiconductor device integrating HVMOS and CMOS. Background technique [0002] Complementary metal oxide semiconductor transistor (CMOS, Complementary Metal Oxide Semiconductor) devices are widely used in the field of microelectronics. Typically used in logic devices, memories, etc. In addition to CMOS, many high-voltage semiconductor transistors that can withstand voltages higher than CMOS are also widely used in the field of microelectronics industry. The most common ones are various types of laterally diffused metal oxide semiconductor transistors (LDMOS, Laterally Diffused Metal Oxide Semiconductor), in addition to LDMOS, there are extended drain metal oxide semiconductor transistors (EDMOS, ExtendedDrain Metal Oxide Semiconductor), Double Diffused Drain Metal Oxide Semiconductor Transistor (DDD-MOS, Double Diffused D...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/08H01L27/092
Inventor 谭健
Owner SUZHOU XYSEMI ELECTRONICS TECH CO LTD
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