Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.

Description

Semiconductor memory device technical field The present invention relates to a semiconductor memory device, and in particular, to an update operation of a DRAM (Dynamic Random Access Memory: Dynamic Random Access Memory). Background technique In recent years, in order to realize SOC (System On Chip) at low cost, high integration is required for DRAM for hybrid loading. Occupying most of the memory area is a memory array having a plurality of memory cells. Heretofore, in order to realize high integration, miniaturization of memory cell area has been carried out by miniaturization technology of memory cell transistors or storage capacitors using high dielectric constant insulating films. For example, in the case of a stack type memory cell, a new high-permittivity insulating film is introduced to ensure capacitor capacitance against the reduction in capacitor area due to miniaturization. However, in order to increase the capacitor capacitance of the memory cell, it is nec...

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