Circuit and application shared by sampling-hold circuit and first stage MDAC operational amplifier

Abstract

The invention relates to production line ADC technology field, and discloses a circuit which is shared by a sample and hold circuit and a first MDAC operational amplifier. The invention includes an operational amplifier, a first switched capacitor unit, a second switched capacitor unit and a third switched capacitor unit. Wherein, the operational amplifier and the first switched capacitor unit form the sample and hold circuit which is used to sample and hold the received the external differential signals shcin1 and shcin2 and to output the obtained differential signals out1_s and out2_s to the first MDAC; the operational amplifier, the second switched capacitor unit and the third switched capacitor unit form the first MDAC which is used to perform residue amplifying for the differential signals out1_s and out2_s received from the sample and hold circuit and to output the obtained differential signals at the same differential signal nodes out1 and out2 at the un-overlapped another clock phase. The invention also discloses a production line ADC circuit which shares the sample and hold circuit and the first MDAC operational amplifier. Using the invention can reduce the circuit power consumption and increase the accuracy of the production line ADC circuit.

Description

technical field [0001] The present invention relates to the technical field of pipelined analog-to-digital converters (Analog to Digital Circuit, ADC), in particular to a circuit shared by a sample-and-hold circuit and a first-stage multiplying digital-to-analog conversion circuit (Multiplying Digital to Analog Circuit, MDAC). And the pipeline ADC shared by the sample-and-hold circuit and the op-amp of the first-stage MDAC circuit is applied. Background technique [0002] ADC is an important part of the mixed-signal system. Among various ADCs, the pipeline ADC is widely used because of its unique compromise advantages in terms of accuracy, speed, power consumption and area. [0003] Such as figure 1 as shown, figure 1 It is a structural schematic diagram of a traditional pipeline ADC. It consists of a front-end sample / hold (S / H) circuit, several sub-stages (STAGE1, STAGE2, ..., STAGE k-1, FLASH), a delay synchronization register array and a digital error correction module...

AI Technical Summary

Problems solved by technology

The op amp of the sampling phase is in the reset state. At this time, although the op amp consumes power, it actually does not work, resulting in a waste of power consumption.

[0008] In addition, the traditional technology of sharing op amps between MDAC circuits cannot eliminate the offset voltage of op amps in the first-stage MDAC, which adds a DC offset to the voltage processed by the second-stage pipeline sub-stage, which affects the accuracy of the pipeline ADC.

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