Flash memory unit structure and preparation thereof
A flash memory cell and manufacturing method technology, applied in electrical components, semiconductor/solid-state device manufacturing, electrical solid-state devices, etc., can solve problems such as threshold voltage drift, affecting applications, metal ion pollution, etc. Effect
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Embodiment 1
[0040] This embodiment provides a flash memory cell structure. Reference attachment figure 2 As shown, it includes a semiconductor substrate 101, a first dielectric layer 102 on the semiconductor substrate 101, a charge storage layer 103 on the first dielectric layer 102, a second dielectric layer 105 on the charge storage layer 103, and The gate 106 on the three-layer stack structure of the first dielectric layer 102 / charge storage layer 103 / second dielectric layer 105" and the semiconductor substrate 101 are located in the “first dielectric layer 102 / charge storage layer 103 / second dielectric layer The source 107 and the drain 108 on both sides of the 105" three-layer stack structure. The charge storage layer 103 includes non-metal discrete atom islands 104.
[0041] In this example, the semiconductor substrate 101 may be various semiconductor materials well known to those skilled in the semiconductor field, including silicon or silicon germanium (SiGe) with a single crystal ...
Embodiment 2
[0057] This embodiment provides a method for fabricating a flash memory cell structure. Reference attachment image 3 Implementation flowchart shown. Step S201, forming a first dielectric layer on the semiconductor substrate; Step S202, forming a charge storage layer on the first dielectric layer, including discrete non-metallic atomic islands; Step S203, forming a second dielectric layer on the charge storage layer; Step S204, annealing; step S205, forming source and drain electrodes on both sides of the three-layer stack structure composed of the first dielectric layer / storage charge layer / second dielectric layer; step S206, forming a gate on the three-layer stack structure pole.
[0058] Figure 4 to Figure 8 It is a schematic structural diagram of an embodiment of the present invention forming a flash memory cell structure. Such as Figure 4 As shown, the first dielectric layer 202 is formed on the semiconductor substrate 201.
[0059] In this example, referring to step S201...
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