Tunneling transistor with barrier

Abstract

The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and / or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Description

technical field [0001] The invention relates to tunnel transistors, in particular to tunnel transistors according to claim 1 . Background technique [0002] As the channel length of metal-oxide-semiconductor field-effect (MOSFET) transistors shrinks to the nanoscale, the short-channel effect becomes more and more significant. Therefore, nanoscale MOSFETs require efficient gate control for good device performance. For this reason, silicon nanowires, "gate all around" or "wrap around" gate transistors have been developed that allow multiple gate levels. [0003] Vertically epitaxial semiconducting nanowire devices have been developed as possible future transistor device candidates. Among the many devices examined, "wrap-around" gate devices have been extensively studied. The device is configured with a ring-shaped gate electrode surrounding the nanowire to control the electrical properties inside the nanowire. [0004] Single crystal nanowires of various semiconductor mate...

AI Technical Summary

Problems solved by technology

[0010] 1. The impurity fluctuations doped in the active region are expected to be large and unavoidable

[0011] 2. The transconductance of the device depends on the length of the gate

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