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Wafer stage package cutting method protecting connection pad

A technology of wafer-level packaging and cutting methods, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., and can solve problems such as manual work, cumbersome packaging process, and unsuitability for mass production.

Inactive Publication Date: 2009-03-18
中国台湾格雷蒙股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of the packaged die produced by this packaging method is slightly larger, and the packaging process is cumbersome, which does not meet the demands of current electronic products that emphasize lightness and small size, and requires individual operations, and even requires manual work, which is not suitable for batch production. Production; moreover, the bottleneck of this packaging technology often occurs in the later cutting process, external mechanical force may cause structural damage, and the particles generated during the cutting process may contaminate the product, resulting in a decline in yield

Method used

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  • Wafer stage package cutting method protecting connection pad
  • Wafer stage package cutting method protecting connection pad
  • Wafer stage package cutting method protecting connection pad

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Embodiment Construction

[0024] Please refer to Figure 1 to Figure 6 , Figure 1 to Figure 6 It is a schematic diagram of a wafer dicing manufacturing method according to a preferred embodiment of the present invention. Such as figure 1 As shown, a first wafer 10 and a second wafer 12 are provided through anodic bonding, eutectic bonding, fusion bonding or plasma activation bonding, etc. A known wafer bonding process bonds the first wafer 10 and the second wafer 12 to form a cap wafer 14 . The first wafer 10 can comprise a standard wafer, a silicon wafer, or a wafer with a defined pattern, and the second wafer 12 can be a glass wafer or a packaged wafer, a silicon wafer, or a wafer of other materials. The choice of the chip 14 is not limited to the bonding of two chips as described in this preferred embodiment, and a single standard chip or a silicon chip can also be used as the upper cover chip 14 .

[0025] Such as figure 2 As shown, a surface pattern definition process is performed to simulta...

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Abstract

The invention discloses a cutting method for protecting the wafer-level packaging of a connecting pad, which comprises forming a plurality of cavities and pre-cutting channels on the front of an upper cover wafer, wherein the depth of each pre-cutting channel is smaller than the depth of each cavity, then bonding the upper wafer and an element wafer whose surface is provided with a plurality of elements and a plurality of connecting pads, then conducting the upper wafer cutting technology, cutting through the upper cover wafer along the pre-cutting channels, removing partial upper cover wafer which is not bonded with the element wafer to expose the connecting pads, finally conducting the element wafer cutting technology to form a plurality of package tube cores.

Description

technical field [0001] The invention relates to a cutting method for wafer-level packaging capable of protecting connection pads, in particular to a cutting method for wafer-level packaging that forms a pre-cut line on an upper cover wafer to simplify the cutting process, improve yield and protect connection pads. Background technique [0002] The packaging of semiconductor components is an important step in its process. The so-called packaging refers to the combination of the core structures in the device. The function of packaging is to protect fragile semiconductor components (such as optical components, micro-electromechanical components, etc.) In the case of environmental damage (such as mechanical damage or particle pollution, etc.), it also takes on the functions of mechanical support and signal output or input. [0003] The known packaging process is as follows: first, the wafer that has completed the processing process is cut and separated into individual dies, and ...

Claims

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Application Information

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IPC IPC(8): H01L21/50
Inventor 蔡君伟邵世丰
Owner 中国台湾格雷蒙股份有限公司
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