High-frequency clock generator, clock frequency conversion method, and chip

Abstract

The invention provides a high-frequency clock generator, a clock frequency conversion method and a chip. The high-frequency clock generator comprises a receiving unit for receiving a low-frequency clock signal; a time-delaying unit for delaying the low-frequency clock signal; a logical gate unit for logical combination of the low-frequency clock signal and the delayed low-frequency clock signal to obtain a high-frequency clock signal; and an output unit for outputting the high-frequency clock signal. The high-frequency clock generator obtains the high-frequency clock signal by combining the time-delaying unit with a logical gate circuit, and has small area and low cost, thereby reducing the cost and the power consumption of the high-frequency clock signal.

Description

technical field [0001] The invention relates to the technical field of clocks, in particular to a high-frequency clock generator, a clock frequency conversion method and a chip. Background technique [0002] In the current application of clock technology, a phase-locked loop (PLL; Phase Lock Loop) is commonly used to convert a low-frequency signal into a high-frequency signal, so as to meet requirements for clock signals in different frequency bands. The main application range of phase locked loop is generally: transmitter, receiver, signal generator, frequency synthesizer, function generator, chip interface, digital circuit, etc. [0003] The existing phase-locked loop is mainly a closed-loop circuit composed of field effect transistors, transistor oscillators, filters, etc., which can generate high-frequency clocks from low-frequency clocks and multiply the frequency by dozens of times for use in digital circuit systems. [0004] However, in the application of some simple...

AI Technical Summary

Problems solved by technology

Therefore, if a phase-locked loop is used in these digital circuits, the cost is relatively high, the power consumption is large, and the occupied area is large, resulting in high cost of digital circuits.

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