Ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube

[0018] A super-junction longitudinal double-diffusion metal oxide semiconductor tube, comprising: an N-type doped silicon substrate that doubles as a drain region, an N-type doped silicon epitaxial layer 2, a cell region 3, and a cell region 3 arranged around the cell region 13 The terminal region 5 and the transition region 4 located between the primitive cell region 3 and the terminal region 5, the N-type doped silicon epitaxial layer 2 is provided on the N-type doped silicon substrate 1, the primitive cell region 3 and the terminal region 5 is set on the N-type doped silicon epitaxial layer 2, and the terminal region 5 of the transistor includes a first super junction structure and an N-type silicon doped semiconductor region 2 , Where the first super junction structure includes an N-type pillar 25 and a P-type pillar 26, in the N-type silicon doped semiconductor region 2 There is a horizontal P-type column 14 and a high-concentration N-type area 12 Wherein, the horizontal P-type pillar 14 may have the same length, or may increase sequentially from bottom to top, and the distance from the left end of the horizontal P-type pillar 14 to the first super junction structure is the same. A high-concentration N-type thin layer 11 is provided on the surface of the first super junction structure and the N-type silicon doped semiconductor region 2, and a field oxide layer is provided on the N-type thin layer 11 18 , In the N-type heavily doped semiconductor region 12 Is connected to the metal layer 12, which is characterized in that in the N-type silicon doped semiconductor region 2 A horizontal P-type pillar 14 is provided and a high-concentration N-type thin layer 11 is provided on the surface of the transistor terminal area 5.

[0019] In this embodiment,

[0020] The transistor cell region 3 is provided with a second super-junction structure. The second super-junction structure includes a P-type pillar 16 and an N-type pillar 15. The P-type pillar 16 of the second super-junction structure is provided with a P-type pillar. The doped silicon semiconductor region 7 and the P-type doped silicon semiconductor region 7 extend into the N-type column 15 adjacent to the P-type column 16, and the P-type doped silicon semiconductor region 7 is provided with N-type heavily doped The source region 6 is provided with a gate oxide layer 18 on the surface of the second super junction structure, the P-type doped silicon semiconductor region 7 and the N-type heavily doped source region 6, and a polysilicon gate 17 is provided on the gate oxide layer 18 and the polysilicon gate 17 is located above the N-type pillar 15 of the second super junction structure, a field oxide layer is provided on the polysilicon gate 17, and the source metal 9 is connected to the N-type heavily doped source region 6.

[0021] A third super junction structure is provided in the transistor transition region 4, and the third super junction structure includes a P-type pillar 16 And N-pillar 15 A low-concentration P-type region 8 is provided above the third super junction structure, and a contact hole is provided on the low-concentration P-type region 8 to connect with the source metal 9.

[0022] Attached below figure 1 , A detailed description of the present invention, as attached figure 1 As shown in the figure, this transistor structure is a vertical device structure. The overall structure includes three parts, namely the cell 3 of the transistor, the transition area 4 of the transistor, and the terminal area 5 of the transistor. The transistor includes an N-type doped silicon lining. Bottom 1, grow a layer of N-type doped silicon epitaxial layer 2 on the N-type doped silicon substrate 1, and then use multiple epitaxy and multiple ion implantation methods to grow the above structure;

[0023] The impurity type of epitaxy is opposite to the impurity type of ion implantation. For N-channel devices, N-type doped epitaxy and P-type doped ion implantation are generally used. figure 1 The structure shown in is the result of four times of epitaxial ion implantation. After each epitaxial growth of an epitaxial layer, a P-type ion implantation is carried out to form a P-type pillar 16. 16, 26 and the horizontal P-type column 14, wherein the length of the horizontal P-type column 14 is gradually increasing with the increase of the number of extensions, that is, the injected area becomes larger and larger, and the length of the horizontal P-type column 14 closest to the surface is the longest ; Multiple epitaxy and ion implantation processes formed the second super junction structure of the transistor cell region 3, the third super junction structure of the transistor transition region 4 and the first super junction structure and the lateral P-type pillar in the transistor terminal region 5 After that, perform another epitaxy, and perform another implantation after the epitaxy to form the P-type doped semiconductor region 8 in the transistor transition region 4 and the P-type doped silicon semiconductor region 7 in the transistor cell region. The type of impurity implanted Contrary to the epitaxial type, after the P-type doped silicon semiconductor region 7 is formed, an ion implantation is used to form the N-type doped source region 6, and finally a high-concentration P-type implantation is performed on the surface of the terminal region of the transistor to form a field The injection layer 11 can effectively suppress the generation of surface leakage current. Then grow the gate oxide layer 16, the polysilicon gate 17, and the polysilicon field plate 10, and the rest are thick field oxygen regions 18 Finally, contact holes are carved out above the N-type doped source region 6 and the P-type doped silicon semiconductor region 7, above the P-type doped semiconductor region 8 and the end of the transistor terminal region 5, and then deposit on both sides Aluminium is deposited and etched to form a source metal contact and extend it to form a metal field plate 9, a drain metal 13 and a metal layer 12. The polysilicon field plate 10 and the source metal extension metal field plate 9 are composed of The field plate structure can effectively increase the breakdown voltage of the surface.

[0024] The above-mentioned transistor cell region is composed of a second super junction structure (including an N-type pillar 15 and a P-type pillar 16), a P-type doped silicon semiconductor region 7 and a source metal 9.

[0025] The transition area of ​​the above-mentioned transistor is composed of a third superjunction structure (including N-type pillar 15 And P-pillar 16 ), a P-type doped semiconductor region 8 and a source metal 9 are formed.

[0026] The above-mentioned transistor terminal region consists of a first super junction structure (including N-type pillar 25 and P-type pillar 26), lateral P-type pillar 14, and N-type silicon-doped semiconductor region ( 2 ), a channel stop ring structure 12, and a field injection layer 11.