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Dynamic boundary scanning chain test method based on programmable devices

A technology of boundary scan and link test, applied in the field of electronic circuit test and boundary scan test of printed circuit assembly board, can solve the problems of increasing the cost of components and printed boards, and achieve the goal of reducing costs and layout expenses Effect

Inactive Publication Date: 2012-05-09
UTSTARCOM TELECOM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

However, while using these devices to manage the boundary scan link on the board, it will undoubtedly increase the cost of components and printed boards

Method used

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  • Dynamic boundary scanning chain test method based on programmable devices
  • Dynamic boundary scanning chain test method based on programmable devices
  • Dynamic boundary scanning chain test method based on programmable devices

Examples

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Embodiment Construction

[0032] The present invention proposes a kind of dynamic, boundary-scan link test method based on PLD, FPGA device, has designed a kind of dynamic boundary-scan link linker (DSCL, DynamicScan Chain Linker), adopts HDL RIL code to DSCL It can be instantiated into a PLD or FPGA programmable device, especially it can be directly instantiated into a programmable device with surplus internal and IO resources on the assembly board to be tested, so as to realize multiple boundary scan chains during boundary scan testing The dynamic loading and unloading of the circuit, so as to test the boundary scan circuit flexibly. The so-called instantiation refers to the use of HDL RIL codes to describe the scan link linker (DSCL) through logic synthesis (synthesis), layout and routing (place & route) into target PLD / FPGA technology library logic units and connections, And finally generate a programming file and upload it to the programmable device.

[0033] Such as figure 1 As shown, the bound...

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Abstract

The invention provides a dynamic boundary scanning chain test method based on PLD and FPGA devices. A dynamic scan chain linker (DSCL) is specialized in a programming device by adopting HDL RIL codes for realizing the dynamic loading and unloading of a plurality of scanning chains, thus limberly testing boundary scanning circuits. The DSCL comprises an IEEE 1149.1 TAP state machine, an instruction order register, an identifier register, a chain control register, a RTI synchronous register, a bypass register and a chain linker so that a test machine can control the chain control register by a testing access port TAP, and the chain linker links the scanning chains hooked on a link scanning port (LSP) according to the value of the chain control register.

Description

technical field [0001] The invention relates to the field of electronic circuit testing, in particular to the field of boundary scan testing of printed circuit assembly boards. Background technique [0002] With the development of the semiconductor industry, the speed and IO density of the signal link on the assembly board are getting higher and higher, and the driving force from the consumer market is increasing the pressure on the area of ​​the assembly board and the time to market, which makes the traditional Structured testing methods are increasingly unable to meet the needs of the assembled board industry. As a new generation of test architecture boundary scan link test, it has attracted more and more attention from the industry. This test architecture provides a series of register controllers inside the silicon chip to realize the requirements for structured testing and control the electrical components on the assembly board. Network for control and visibility. Toda...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G01R31/317
Inventor 王庆翔
Owner UTSTARCOM TELECOM CO LTD
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