Method for manufacturing gate structure

Abstract

The invention discloses a method for manufacturing a gate structure, which comprises the steps: firstly, a substrate is supplied, a gate dielectric layer is formed on the substrate, and at least one dielectric post is formed on the gate dielectric layer; secondly, a polycrystalline silicon layer is formed above the substrate in adaptability to cover the dielectric post and the gate dielectric layer; thirdly, an etching technology is carried out, the partial polycrystalline silicon layer is removed, and two polycrystalline silicon clearance walls are formed on the side wall of the dielectric post; fourthly, an etching stop layer is formed on the substrate, and a dielectric layer is formed to cover the etching stop layer, the two polycrystalline silicon clearance walls and the dielectric post; fifthly, the dielectric post and the dielectric layer are partially removed, the surfaces of the dielectric post and the dielectric layer are lower than the surface of a polycrystalline silicon post; and sixthly, a metal silicide self-aligning technology is carried out to convert the polycrystalline silicon post into a metal silicide post.

Description

technical field [0001] The present invention relates to a semiconductor process, and in particular to a manufacturing method of a gate structure. Background technique [0002] Photolithography is one of the most important steps in the entire semiconductor process. Anything related to the structure of semiconductor elements, such as the pattern of each layer of thin film, is determined by the photolithography process to determine the size of its Critical Dimension (CD), which is also determined by the development of photolithography process technology. [0003] For a metal oxide semiconductor transistor (MOS Transistor), one of the most important components is the gate, which is used to control the on / off of the channel, and it is located on the device area of ​​the substrate. In many types of electronic products, the gates in the device area are parallel to each other, and the line width thereof is a critical dimension in the semiconductor process. [0004] With the increa...

AI Technical Summary

Problems solved by technology

However, such exposure tools are still expensive, or are still in development

[0005]In addition, in order to reduce the size of the components, photoresist materials with thinner thickness and high sensitivity (Sensitivity) can also be used in the photolithography process layer, but this process will affect the subsequent etching process and cannot reduce the size of the component

On the other hand, the economic applicability of photomask cost has also become a major problem when the component size is continuously reduced to reach the Deep Submicron process in order to increase the integration level of integrated circuits.

Images