Packaging method of improving antistatic capability of integrated circuit chip

Abstract

The invention discloses a packaging method of improving the antistatic capability of an integrated circuit chip. The method comprises the steps: producing a power cord loop and a ground cord loop on a packaging tube shell; connecting one or a plurality of capacitors and a resistor between the power cord loop and the ground cord loop; leading one or a plurality of positions of the integrated circuit chip, which are connected with a power cord inside the chip to the power cord loop; and leading one or a plurality of positions of the integrated circuit chip, which are connected with a ground cord inside the chip to the ground cord loop. The invention enables chips with poor electrostatic discharge (ESD) protection capability inside the integrated circuit chip to reach good ESD protection capability after packaging.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a packaging method for improving the antistatic capability of integrated circuit chips. Background technique [0002] With the development of the semiconductor industry, especially after entering the deep submicron scale, on the one hand, the breakdown voltage of the oxide layer will be greatly reduced; on the other hand, some manufacturers adopt the silicon-on-insulator SOI technology. , the channel for discharging the electrostatic discharge protection (ESD) current is narrow, and the heat dissipation capability is relatively poor, so that the anti-ESD ability of the output tube is very poor, and even has to be output in a complementary metal oxide semiconductor (CMOS) A small resistor is connected in series between the diodes that discharge the ESD current to improve the anti-ESD capability of the output tube. [0003] Since it is necessary to design a structu...

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Problems solved by technology

[0007] In view of this, the present invention is aimed at the problems referred to above, and provides a kind of encapsulation method that improves antistatic ability of integrated circuit chip, and this method is relatively poor for some self ESD protection ability, but each pressure welding pad (PAD) and VDD / VSS inside the chip Diodes (751, 752, 753, 754) placed between them are very effective when their forward-bias conduction capability is very good; when the ESD current comes, due to the effect of the capacitor absorbing the ESD current, the voltage across the capacitor is limited to much lower than The level of the working voltage of the circuit. Therefore, except for the diode participating in the discharge current, all other MOS tube structures are in a non-breakdown state (closed, MOS tube on / sub-open state), and the purpose of protecting the chip circuit is achieved.

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