8T low leakage sram cell
A drain and inverter technology, applied in the field of static random access memory, can solve the problem of slowing down the working speed of the unit
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[0015] The present invention proposes an 8TSRAM cell capable of reducing leakage current without sacrificing operating speed.
[0016] figure 2 A circuit diagram of an 8T low-leakage SRAM cell is shown according to one embodiment of the present invention. exist figure 1 Two NMOS transistors 215 and 225 are added to the conventional 6T SRAM cell 100 shown in FIG. 2 to form the SRAM cell 200 . The sources and drains of the NMOS transistors 215 and 225 are connected to the power ground and the node V, respectively. Node V becomes the virtual ground for cell 100 in 8T SRAM cell 200 . Obviously, the functions of the elements of the SRAM cell 200 , such as data storage, are still performed by the cell 100 contained in the cell 200 .
[0017] refer again figure 2 , since the gate of the NMOS transistor 215 is connected to its drain, the NMOS transistor 215 functions as a forward-biased transistor diode, and the voltage drop between its drain and source is maintained as the thr...
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