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8T low leakage sram cell

A drain and inverter technology, applied in the field of static random access memory, can solve the problem of slowing down the working speed of the unit

Active Publication Date: 2012-10-03
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this technique also slows down the operation of the cell if the word lines are used to control the virtual ground of each row

Method used

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  • 8T low leakage sram cell
  • 8T low leakage sram cell
  • 8T low leakage sram cell

Examples

Experimental program
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Embodiment Construction

[0015] The present invention proposes an 8TSRAM cell capable of reducing leakage current without sacrificing operating speed.

[0016] figure 2 A circuit diagram of an 8T low-leakage SRAM cell is shown according to one embodiment of the present invention. exist figure 1 Two NMOS transistors 215 and 225 are added to the conventional 6T SRAM cell 100 shown in FIG. 2 to form the SRAM cell 200 . The sources and drains of the NMOS transistors 215 and 225 are connected to the power ground and the node V, respectively. Node V becomes the virtual ground for cell 100 in 8T SRAM cell 200 . Obviously, the functions of the elements of the SRAM cell 200 , such as data storage, are still performed by the cell 100 contained in the cell 200 .

[0017] refer again figure 2 , since the gate of the NMOS transistor 215 is connected to its drain, the NMOS transistor 215 functions as a forward-biased transistor diode, and the voltage drop between its drain and source is maintained as the thr...

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Abstract

This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line.

Description

technical field [0001] The present invention relates generally to static random access memories, and more particularly to dual port SRAM cells. Background technique [0002] For example, semiconductor memory devices include static random access memory, or SRAM, and dynamic random access memory, or DRAM. A DRAM memory cell has only one transistor and one capacitor, so its integration level is high. But DRAM needs to be constantly updated, so its power consumption and low speed limit its application mainly as a computer's main memory. An SRAM cell, on the other hand, is bistable, which means it maintains its state as long as it is supplied with enough power. SRAM can work in a state of higher speed and lower power consumption, so all high-speed cache memories (cache) of computers use SRAM. Other applications of SRAM include embedded memory and network device memory. [0003] A conventional SRAM cell is known as a six-transistor cell (6T), which includes six metal-oxide-sem...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/412
CPCG11C11/412G11C8/16
Inventor 黄怀莹林祐宽洪圣强王屏薇
Owner TAIWAN SEMICON MFG CO LTD