Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof

A gate dielectric layer and manufacturing method technology, applied in the field of gate dielectric layer and its manufacturing, can solve the problems of inability to form semiconductor devices with different performances and inability to control nitrogen distribution

Inactive Publication Date: 2010-01-06
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
View PDF1 Cites 17 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the plasma nitridation process cannot control the distribution of nitrogen doped in the silicon oxide layer, and it is impossible to form a certain distribution of nitrogen-containing silicon oxide purposefully.
Therefore, it is impossible to form semiconductor devices with different performances

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof
  • Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof
  • Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0055] Figure 4 to Figure 5 It is a schematic cross-sectional view of structures corresponding to each step of the manufacturing method of the first embodiment of the manufacturing method of the gate dielectric layer of the present invention.

[0056] Please refer to Figure 4 , firstly, a substrate 10 is provided, and a silicon oxide layer 12 is provided on the substrate 10 .

[0057] Wherein, the substrate 10 may be a semiconductor material, such as one of single crystal silicon, polycrystalline silicon or amorphous silicon, or may be a silicon on insulating layer (Silicon On Insulator, SOI) structure or an epitaxial layer structure on silicon. N-type impurities or P-type impurities may be doped into the substrate 10 .

[0058]The method for forming the silicon oxide layer 12 includes but not limited to high temperature furnace tube oxidation, rapid thermal annealing oxidation or in-situ steam generation oxidation (ISSG) process.

[0059] Before forming the silicon oxide...

Embodiment 2

[0073] Through one ion implantation and nitridation process, the nitrogen in the silicon oxide layer may not be able to achieve the desired distribution. In this embodiment, the ion implantation and nitridation process can be divided into multiple times. Optionally, in each ion implantation and nitridation process, the implantation energy or implantation dose is different, or the implantation energy and dose are both different, so as to form a silicon oxide layer with nitrogen concentration distribution meeting the requirements. I won't go into details here.

Embodiment 3

[0075] With the continuous improvement of the semiconductor manufacturing process, the thickness of the gate dielectric layer is getting thinner; correspondingly, when forming the gate dielectric layer of the nitrogen-containing silicon oxide layer, the thickness of the silicon oxide layer is also continuously thinning, for example, in At the 65nm technology node, the thickness of the silicon oxide layer is only 12A, and at 45nm, the thickness of the silicon oxide layer will be even thinner. For such a thin silicon oxide layer, when the ion implantation nitridation process is adopted, the implanted nitrogen ions may penetrate the silicon oxide layer, thereby affecting the film characteristics of the formed gate dielectric layer. In this embodiment, the problem of nitrogen ions penetrating the silicon oxide layer is improved by first forming a buffer layer on the silicon oxide layer to be doped.

[0076] Figure 6 to Figure 8 It is a schematic cross-sectional view of the struc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for forming a gate dielectric layer, which comprises the following steps: providing a substrate which is provided with a silicon oxide layer; and executing nitriding process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer, wherein the nitriding process at least comprises a step of ion implantation nitriding process. The invention also provides the gate dielectric layer, a semiconductor device and a manufacturing method thereof. The method can adjust the distribution of nitrogen in the gate dielectric layer according to requirements.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a gate dielectric layer and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof. Background technique [0002] Since the invention of the metal oxide semiconductor transistor, silicon oxide has been used as the most important material of the gate dielectric layer due to its good integration characteristics with silicon and polysilicon. With the improvement of integration, the size of the gate is getting smaller and smaller. Correspondingly, the thickness of the silicon oxide layer as the gate dielectric layer also needs to be continuously reduced, which has a great impact on the thickness uniformity and defect control of the formed silicon oxide layer. And the requirements for film characteristics such as anti-breakdown ability are getting higher and higher, which puts forward higher requirements for the manufacturing proc...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/28H01L21/336H01L21/3115H01L29/51H01L29/78
Inventor 吴汉明高大为
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com