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Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects

A substrate and bonding technology, used in welding equipment, manufacturing tools, electrical solid devices, etc., can solve problems such as erosion of metal linings, device reliability problems, porosity, etc., to reduce process time, eliminate complexity, improve Effect of RC Delay Time

Inactive Publication Date: 2010-03-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This oxide and / or contamination layer may be porous and moisture may then attack the metal pad, causing device reliability issues

Method used

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  • Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects
  • Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects
  • Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects

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Embodiment Construction

[0020] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the illustrative embodiments provide many applicable inventive concepts that can be embodied in a wide variety of embodiments. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0021] An advantage of the illustrative embodiments is that the illustrative embodiments provide a 3D IC with little or no low-k damage and a small gap thickness between the first and second substrates. According to an exemplary embodiment, the gap may be between about 1 μm and 5 μm.

[0022] figure 1 A cross-sectional view of a three-dimensional semiconductor integrated circuit (3D IC) interconnect formed by a direct metal bonding process. In this example, the first substrate 102 may include a semiconductor wafer, semiconductor die, other substrate, flip chip...

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PUM

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Abstract

An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.

Description

technical field [0001] The present invention relates to substrate-to-substrate bonding apparatus and methods for three-dimensional (3D) interconnections, and more particularly, to apparatus and methods for direct metal bonding. Background technique [0002] As the cost of shrinking semiconductor devices continues to increase, alternative approaches are being explored, such as extending circuit integration to three dimensions or semiconductor substrate stacking. Bonding two or more substrates together to form a three-dimensional structure. Various bonding processes have been applied to these structures. [0003] Adhesive bonding and dielectric fusion bonding are bonding processes that bond dielectric layers together. Adhesive bonding and dielectric fusion bonding are commonly used in processes that require further processing steps after bonding, such as through-via etch processes. Another method of bonding is traditional direct metal bonding, which bonds the metal of one s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/00H01L21/50H01L21/60
CPCH01L2224/8101H01L2924/01082H01L2924/0105H01L24/81H01L2924/01079H01L2224/81054H01L2224/81801H01L2224/81011H01L24/13H01L2924/30105H01L2924/14H01L2924/01019H01L2924/01033H01L2924/01006H01L2924/01029H01L2224/75H01L24/16H01L2924/01075H01L24/64H01L2224/81205H01L24/75H01L2224/75301H01L2924/01013H01L2224/751H01L2224/81894H01L2224/056Y10T29/53174H01L2924/00014B23K1/06
Inventor 余振华邱文智吴文进
Owner TAIWAN SEMICON MFG CO LTD
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