High voltage low resistance MOSFET device and its manufacture method

Abstract

The invention discloses a high voltage NMOS using the tagma double-times doping way, wherein the second time doping is performed by the self-alignment and the step phenomenon in the channel is eliminated and the device performance is increased.

Description

technical field [0001] The invention relates to a metal oxide semiconductor field effect transistor (MOSFET), in particular to a low-resistance high-voltage N-type MOSFET (NMOS). Background technique [0002] For lateral high-voltage MOSFETs fabricated in BiCMOS or BCDMOS processes, low on-resistance and high voltage are the two main design factors. figure 1 A conventional lateral type high voltage NMOS is shown. Figure 2A , 2B show two process steps in the manufacturing process used to describe the structural characteristics of the traditional high-voltage N-type MOSFET (NMOS). Such as figure 1 As shown, the high-voltage NMOS includes a P-type substrate with a P-well and an N-well on the P-type substrate. The NMOS further includes a gate G composed of an oxide layer 11 and a polysilicon layer 12 , an N+ source region S and an N+ drain region D. Such as Figure 2A As shown, in the conventional process, the P-well is formed by doping the N-well oxide layer 20 as a barri...

AI Technical Summary

Problems solved by technology

In this way, the step will sit above the channel of the NMOS, which is in the figure 1 The top is the dotted line area where the P well and the gate overlap. This step makes the channel curved, which will hinder the flow of electrons in the channel, so the on-resistance will increase.

In addition, the elongated NMOS channel further increases the on-resistance

Images