73 results about "High voltage mosfet" patented technology

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions.

A composite high voltage schottky rectifier is revealed that provides a forward voltage slightly larger than a low voltage schottky rectifier combined with a high voltage breakdown capability. The composite rectifier can be formed from the combination of a low voltage schottky rectifier, a high voltage mosfet, and a few small passive components. A quarter bridge primary switching network similar in some ways to a half bridge primary switching network is revealed. The quarter bridge network consists of four switches with voltage stress equal to half the line voltage and the network applies one quarter of the line voltage to a primary magnetic circuit element network thereby reducing the number of primary winding turns required to one quarter by comparison to a common full bridge network. A synchronously switched buck post regulator is revealed for multi-output forward converters. The synchronously switched buck post regulator accomplishes precise independent load regulation for each output and reduced magnetics volume by using a coupled inductor with a common core for all outputs plus a second smaller inductor for each output except the highest voltage output. An improved capacitor coupled floating gate drive circuit is revealed that provides an effective drive mechanism for a floating or high side switch without the use of level shifting circuits or magnetic coupling. The capacitor coupled floating gate drive circuit is an improvement over prior art capacitor coupled floating gate drive circuits in that the new circuit uses a positive current feedback mechanism to reject slowly changing voltage variations that cause unintentional switch state changes in prior art capacitor coupled floating gate drive circuits.

An n well region and an n⁻region surrounding the n well region are provided in the surface layer of a p⁻silicon substrate. The n⁻region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p⁻ opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p⁻opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

The invention is concerned with high voltage MOSFET device. There is deep n-wells on P or N tape underlay, at least the first n-well, the second n-well and the first and second p-well, and n-well and p-well have n+ adulteration area or p+ adulteration area, and the source or drain is leading from n+ adulteration area or p+ adulteration area. Usually, grid is leading from poly Si gate covering the thin gate oxide area of n-well or p-well, and there is at least one STI low groove insulation coating between source and drain, while poly Si gate extends to STI area. There is a layer low impurity p type underlay between high voltage drain and the second p-well to prevent the possible breakdown. The high voltage MOSFET device isolated with low groove can combine the breakdown protection characteristics to normal submicron CMOS without changing existing CMOS process.

The invention discloses a high voltage NMOS using the tagma double-times doping way, wherein the second time doping is performed by the self-alignment and the step phenomenon in the channel is eliminated and the device performance is increased.

The invention relates to a tri-level bidirectional DC/DC circuit. The circuit comprises an MOSFET tube M1, an MOSFET tube M2, an MOSFET tube M3, an MOSFET tube M4, a flying capacitor, a diode and an inductor. The drain electrode of the MOSFET tube M1 is connected with the positive electrode of a cell. The drain electrode of the MOSFET tube M2 is connected with the source electrode of the MOSFET tube M1. The source electrode of the MOSFET tube M2 is connected with the negative electrode of the cell. The source electrode of the MOSFET tube M3 is connected with the drain electrode of the MOSFET tube M1. The source electrode of the MOSFET tube M4 is connected with the drain electrode of the MOSFET tube M3. The drain electrode of the MOSFET tube is connected with one end of a direct-current bus. One end of the flying capacitor is connected with the drain electrode of the MOSFET tube M3. The other end of the flying capacitor is connected with the source electrode of the MOSFET tube M1. The source electrode of the MOSFET tube M1 is connected with the middle point of the direct current bus through the inductor and the diode. The other end of the direct current bus is connected with the source electrode of the MOSFET tube M2. According to the invention, a low-voltage grade MOSFET can be used for replacing a high-voltage grade MOSFET, so the disadvantage of the quite poor performance parameters of the high-voltage MOSFET device is overcome; switching loss of the switch tube can be reduced; and the switch tube can be prevented from being damaged.

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

The invention relates to semiconductor technologies, in particular to a laterally high-voltage MOSFET and a manufacturing method thereof. The laterally high-voltage MOSFET is characterized in that a first-kind conduction type semiconductor field dropping layer is formed in a second conduction type semiconductor drift region through photoetching and ion implantation technologies, and a second conduction type semiconductor heavy doping layer is formed on the surface of the second conduction type semiconductor drift region through the photoetching and ion implantation technologies. The laterally high-voltage MOSFET has the advantages that under the circumstance that high breakdown voltage is guaranteed, specific on-resistance of the MOSFET can be greatly reduced, meanwhile the electric field peak value of the source end of the laterally high-voltage MOSFET is reduced, high-field effects are avoided, breakdown voltage of the MOSFET is improved, the MOSFET has lower on-resistance and a smaller chip area under the condition of the same breakover capacity, and a surface electric field of the MOSFET is well optimized; meanwhile, the manufacturing method is simple, low in technological difficulty and especially suitable for the laterally high-voltage MOSFET.

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

The present invention relates to an integrated circuit (semiconductor device) for which consolidation of a fine CMOS and a medium/high-voltage MOSFET is assumed to be carried out. A feature of the present invention is a small width (channel length) of a channel region CH. Specifically, when the width of the channel region planarly overlapped with a gate electrode is “L” and the thickness of the gate electrode is “t”, the channel region is formed to have the width of the channel region being larger than or equal to ⅕ times the thickness t of the gate electrode and smaller than or equal to the thickness t. Thus, the width L of the channel region can be reduced, and variations in the threshold voltage can be reduced.

Circuits and methods to achieve a regulated analog switch being capable to provide an output-voltage not exceeding a defined limit are disclosed. In a preferred embodiment a car battery provides a supply voltage up to 40 Volts, wherein a load must not have an output voltage higher than 22 Volts. The drain-source ON-resistance of the switch, realized by a high-voltage MOSFET, is kept to a minimum. The voltage regulation of the preferred embodiment is performed by a single stage operational amplifier and a two-stage amplifier having Miller compensation.

The invention discloses a high-voltage MOSFET current sampling circuit which comprises an on-off control module, a voltage sampling module, a voltage/current conversion module and a voltage output module. The on-off control module controls a sampling time point of the current sampling circuit. The voltage sampling module obtains sampling voltage. The voltage/current conversion module converts the sampling voltage into sampling currents, and then the voltage output module outputs the corresponding voltage. According to the high-voltage MOSFET current sampling circuit, the voltage difference between a drain electrode and a source electrode of a high-voltage power MOSFET switching device is directly sampled so as to judge the currents flowing through the high-voltage power MOSFET switching device, and the problem that due to the fact that in the traditional technology, a sampling element is additionally arranged, power loss is caused is solved; meanwhile, on-off of the on-off control module is controlled through a time sequence signal so that the current sampling circuit can adapt to different input voltage ranges, the precision of the sampled currents is improved, and the production cost is reduced.

The invention provides a laminated electric field modulation high-voltage MOSFET structure and a method for manufacturing the same. The MOSFET structure includes a semiconductor substrate provided with the epitaxial layer of a laminated electric field modulation structure and the metal-oxide-semiconductor (MOS) structure on the laminated electric field modulation. The laminated electric field modulation is an N/P/N/P structure composed of alternate n-type semiconductors and p-type semiconductors. The N/P structure and the semiconductor substrate have the same material. The N-doped region and the P-doped region in the layer are aligned to each other. The invention provides different methods for manufacturing the electric field modulation structure, including a high-energy ion implantation method, an etching deep groove and filling method, and an etching deep groove and sidewall ion implantation method, thereby laying the foundation for the fabrication of a device. The MOSFET obtained by the technical scheme in the invention not only inherits advantages of increasing blocking voltage and decreasing on-resistance of a traditional semi-super junction structure, but also reduces the difficulty of processing technology of each electric field modulation structure layer.

A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in a split gate device is formed using about the same overall thermal budget while forming in parallel a thick gate oxide for a an embedded high voltage MSOFET device.