CMP slurry and a polishing method using the same

Abstract

The present invention relates to a CMP slurry that is able to reduce dishing generation, when it is applied to polishing or planarization of silicon oxide layer, for example, and a polishing method. The CMP slurry includes a polishing abrasive, a linear anionic polymer, a compound including a phosphoric acid group, and water, and the ratio of CMP polishing speed to a silicon oxide layer : CMP polishing speed to a silicon nitride layer is 30:1 to 50:1.

Description

technical field [0001] The present invention relates to a slurry (CMP) for chemical mechanical polishing (hereinafter "CMP slurry") and a method of polishing using the slurry. In particular, the present invention relates to a CMP slurry capable of reducing dishing when used to polish or planarize, for example, a silicon oxide layer, and to a method of said polishing. Background technique [0002] A LOCOS (Local Oxidation of Silicon) method of selectively growing a silicon oxide layer on a semiconductor substrate and forming a device isolation layer has hitherto been used as a device isolation technique. However, when making semiconductor devices highly integrated and miniaturized, the LOCOS method has limitations in reducing the width of the device isolation layer. Therefore, the STI (Shallow Trench Isolation) method was introduced, by forming on the semiconductor substrate. The trench is filled with an insulating layer (such as a silicon oxide layer) inside the trench to d...

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Problems solved by technology

[0007] However, when the polishing selectivity in the CMP method is too high, dishing occurs, and the device properties may deteriorate due to over-polishing of the silicon oxide layer filled in the trench

In particular, dishing issues cause stepped defects between active and field regions in ultra-miniaturized devices with trench line widths of 50 nm or less, and have adverse effects on device performance and reliability

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