Method for forming asymmetrical transistor

Abstract

The invention relates to a method for forming an asymmetrical transistor. The method comprises the following steps of: providing a substrate which comprises an active region; forming a grid structure on the surface of the active region; forming a drain electrode region, a source electrode region and a groove region between the source electrode region and the drain electrode region in the active region and at two sides of the grid structure; forming a dielectric layer covering the drain electrode region, the source electrode region and the grid electrode region on the surface of the substrate; forming a photoresist graph on the surface of the dielectric layer; sequentially etching the dielectric layer by using the photoresist graph as a mask until a first groove exposed out of the drain electrode region and a second groove exposed out of the source electrode region are formed, wherein the line width of the second groove is larger than that of the first groove; carrying out ion implantation on the groove region by using the photoresist graph as a mask to form a pocket region, wherein the pocket region is adjacent to the source electrode region, and the doping type of the pocket region is opposite to the source electrode region; and forming metal plugs in the first groove and the second groove. The invention can save the cost of masks and reduces the process steps.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming an asymmetric transistor. Background technique [0002] Low Power Dynamic Random Access Memory (LPDRAM) is widely used in mobile phones, digital players (Digital Player), personal digital assistants (Personal Digital Assistant, PDA) and other fields due to its excellent low power consumption. [0003] An important parameter to measure the performance of low-power dynamic random access memory is the refresh time (Refresh Time) of low-power dynamic random access memory. The memory consumes less power. [0004] For DRAM, there are two ways to increase the refresh time, one is to increase the capacitance of the memory cell, and the other is to reduce the leakage current of the memory cell. [0005] The transistor structure of an asymmetric memory cell is applied to reduce the leakage current of the memory cell. More information about the preparation o...

AI Technical Summary

Problems solved by technology

[0006] The existing process for forming the transistor structure of the memory cell with an asymmetric structure requires an additional step of forming the pocket region 130 in addition to the steps of the existing transistor process, and the step of forming the additional pocket region 130 requires Mask plate, increase cost input

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