Method for manufacturing lengthwise region of CoolMOS

[0036] Taking a PMOS-based CoolMOS device as an example, the manufacturing method of the CoolMOS of the present invention includes the following steps:

[0037] In the first step, an epitaxial process is used to grow a lightly doped N-type epitaxial layer 11 on the heavily doped N-type silicon substrate 10. The epitaxial process is to deposit a single crystal layer on a single crystal substrate, usually using chemical vapor deposition (CVD) equipment.

[0038] In the second step, using a photolithography process, an ion implantation window 110 is defined on the epitaxial layer 11, and the position of the ion implantation window 110 is the position of the P-type longitudinal region of the CoolMOS device. Defining the ion implantation window 110 means that after the photoresist 20 is coated on the silicon wafer, the photoresist 20 above the ion implantation window 110 is removed through steps such as exposure and development, and the photoresist 20 in the remaining area is retained.

[0039] In the third step, an ion implantation process is used to implant P-type impurities into the ion implantation window 110 to form a P-type longitudinal region 12, and then an annealing process is performed.

[0040] Repeat the above steps 1-3 until the epitaxial layer 11 reaches the thickness a', and the total epitaxial layer formed at this time is the first epitaxial layer 11. The total longitudinal zone formed at this time is the first longitudinal zone 12, and the height is a. The bottom of the first longitudinal region 12 is on or above the lower surface of the first epitaxial layer 11, that is, a≤a'.

[0041] Please refer to steps 1-3 above image 3 As shown, please refer to steps 4-6 below Figure 5.

[0042] The fourth step is to use an epitaxial process to grow a second epitaxial layer (lightly doped N-type) 21 on the first epitaxial layer 11. The thickness of the second epitaxial layer 21 is b, and a'+b is required by the CoolMOS device The thickness of the epitaxial layer.

[0043] In step 5, using photolithography and etching processes, trenches 210 are etched in the second epitaxial layer 21. The position of the trenches 210 is the position of the P-type longitudinal region, and the bottom of the trench 210 or the first P-type The upper surface of the longitudinal zone 12 (e.g. Figure 5 As shown), or below the upper surface of the first P-type longitudinal region 12 (that is, part of the first P-type longitudinal region 12 can be etched away).

[0044] In the sixth step, P-type monocrystalline silicon is deposited in the trench 210 by an epitaxial process, and the trench 210 is filled. The deposited P-type monocrystalline silicon forms a second P-type vertical region 22 in the trench 210. The total height of the two P-type vertical regions 22 and the remaining first P-type vertical region 21 is the height of the P-type vertical region required by the CoolMOS device.

[0045] At this time, the vertical region of the CoolMOS device has been fabricated, and then a silicon dioxide layer is deposited on the second epitaxial layer 21 as a gate oxide layer, and then a polysilicon layer is deposited on the silicon dioxide layer, and then The polysilicon gate is etched by photolithography and etching processes. Next, an ion implantation process is used to form a P-type body implantation area on both sides of the polysilicon gate. Finally, an ion implantation process is used to form N-type source implantation regions on both sides of the polysilicon gate. This step is exactly the same as the polysilicon gate structure fabrication, P-well implantation, and source implantation processes in the CMOS process. Finally, N-type and P-type CoolMOS devices are formed on the surface (lateral) and inside (vertical) of the silicon wafer.

[0046] In steps 1-3 of the above method, the epitaxial layer 11 epitaxially grown multiple times has the same N-type impurity concentration, so that the first epitaxial layer 11 becomes a whole with uniform impurity concentration. In the fourth step of the above method, the epitaxially grown second epitaxial layer 21 has the same N-type impurity concentration as the first epitaxial layer 11, so that the second epitaxial layer 21 and the first epitaxial layer 11 become a whole with uniform impurity concentration. It constitutes a complete epitaxial layer of the CoolMOS device.

[0047] In steps 1-3 of the above method, the P-type vertical region 12 implanted multiple times has the same P-type impurity concentration, so that the first P-type vertical region 12 becomes a whole with uniform impurity concentration. In the fourth step of the above method, the epitaxially deposited second P-type vertical region 22 has the same P-type impurity concentration as the first P-type vertical region 12, so that the second P-type vertical region 22 and the first P-type vertical region 12 It becomes a whole with uniform impurity concentration and constitutes a complete P-type vertical region of the CoolMOS device.

[0048] For CoolMOS devices with vertical regions of any height, in principle, the present invention first considers the use of epitaxial growth + trench etching + epitaxial deposition filling process to manufacture the vertical regions. If the process is not sufficient to form a complete and void-free vertical region, after subtracting the maximum height of the void-free vertical region that can be formed by the process, it is manufactured by one or more epitaxial growth + ion implantation processes.

[0049] In actual production, the present invention first performs a predetermined number of times (determined by the calculation result) epitaxial growth + ion implantation process to produce a part of the height of the vertical region, and then uses the epitaxial growth + trench etching + epitaxial deposition filling process to produce the remaining part of the height of the vertical region Zone, which ultimately forms a full-height longitudinal zone.

[0050] Let the height of the vertical region required by the CoolMOS device be x, Δa is the height of the vertical region that can be manufactured by an epitaxial growth + ion implantation process, and b is the vertical region without voids that can be manufactured by an epitaxial growth + trench etching + epitaxial deposition filling process. The zone height is set, and c is the number of times that the epitaxial growth + ion implantation process is used. For any x, when x≤b, the vertical region of the CoolMOS is manufactured by an epitaxial growth + trench etching + epitaxial deposition filling process. When x>b, then c=(x-b)/Δa, when c has a decimal, it is rounded up, and if c is calculated as 3.01, it is rounded up c=4. For example, x=46μm, Δa=5μm, b=30μm, then c=4. When actually manufacturing a CoolMOS device with a 46μm height vertical region, first use 4 epitaxial growth + ion implantation processes to manufacture a 16-20μm height first vertical region, and then use an epitaxial growth + trench etching + epitaxial deposition filling process A second longitudinal zone with a height of 26-30 μm is produced.

[0051] The CoolMOS devices in the above-mentioned embodiments are all based on PMOS, and the present invention can also be applied to manufacturing the vertical region of CoolMOS based on NMOS, except that the doping types (P-type, N-type) of each part are interchanged.