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Method for manufacturing lengthwise region of CoolMOS

A manufacturing method and vertical technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex process, high processing cost, and long process time, so as to overcome voids, improve process efficiency, and improve process overly complex effects

Active Publication Date: 2011-03-23
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, this method has complicated process, long process time and high processing cost.

Method used

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  • Method for manufacturing lengthwise region of CoolMOS
  • Method for manufacturing lengthwise region of CoolMOS
  • Method for manufacturing lengthwise region of CoolMOS

Examples

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Embodiment Construction

[0036] Taking the CoolMOS device based on PMOS as an example, the manufacturing method of CoolMOS of the present invention includes the following steps:

[0037] In the first step, a lightly doped N-type epitaxial layer 11 is grown on the heavily doped N-type silicon substrate 10 by using an epitaxial process. The epitaxial process is to deposit a single crystal layer on a single crystal substrate, usually using chemical vapor deposition (CVD) equipment.

[0038] In the second step, an ion implantation window 110 is defined on the epitaxial layer 11 by using a photolithography process, and the position of the ion implantation window 110 is the position of the P-type vertical region of the CoolMOS device. The so-called definition of the ion implantation window 110 means that after the photoresist 20 is coated on the silicon wafer, the photoresist 20 above the ion implantation window 110 is removed through steps such as exposure and development, and the photoresist 20 in the rem...

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PUM

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Abstract

The invention discloses a method for manufacturing a lengthwise region of a CoolMOS, and the lengthwise region is manufactured by two steps as follows: manufacturing a lengthwise region with a certain height by adopting a primary or repeated epitaxial growth technology and an ion implantation technology; and manufacturing a lengthwise region with the rest height by adopting an epitaxial growth technology, a groove etching technology and an epitaxial depositing and filling technology, thus finally forming a lengthwise region with a complete height. On the basis, polysilicon gate structures can be manufactured, and plasma implantation and ion source implantation are carried out to finally form a CoolMOS device. The method in the invention has high process efficiency, and no holes exist in the lengthwise region.

Description

technical field [0001] The invention relates to a manufacturing process of a semiconductor device, in particular to a CoolMOS manufacturing process. Background technique [0002] CoolMOS is a new type of high-voltage MOS tube, also known as a superjunction (Superjunction) MOS tube. Its advantage is that it can provide an order of magnitude smaller on-resistance than traditional high-voltage MOS tubes while working under high voltage; in addition to low on-resistance, it also has the advantages of low power consumption and low switching time. [0003] see figure 1 , which is a schematic diagram of the basic structure of CoolMOS. A layer of lightly doped N-type epitaxial layer 11 is grown on heavily doped N-type silicon substrate 10 , and there is a P-type vertical region 12 in the epitaxial layer 11 . The P-type vertical region 12 is up against the upper surface of the epitaxial layer 11 , and down to the inside of the epitaxial layer 11 or the interface between the epitax...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/20H01L21/265H01L21/306
Inventor 刘远良张帅
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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