Silicon on insulator (SOI) wafer and formation method thereof

Abstract

The invention relates to a silicon on insulator (SOI) wafer and a formation method thereof, wherein the formation method of the SOI wafer comprises the following steps: providing a monocrystalline silicon chip on which a mask layer is formed; etching the mask layer and the monocrystalline silicon chip to form a plurality of grooves; forming first insulating layers on the side walls and bottoms ofthe grooves; etching to remove the first insulating layers on the bottoms of the grooves; etching the monocrystalline silicon chip under the grooves along the grooves to form holes; treating the inner walls of the holes to form second insulating layers; and filling insulating material layers in the grooves and the hoes. The SOI wafer has simple process, low manufacturing cost and high quality, and is compatible with the manufacture procedure of the standard silicon CMOS process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SOI wafer and a forming method thereof. Background technique [0002] Currently, SOI (Silicon on Insulator, silicon on insulator) wafers are widely regarded as semiconductor substrates that can improve the performance of semiconductor devices. The SOI wafer includes a silicon base, an insulating insulating layer, and a top silicon layer. Such a structure has the following advantages: (1) It can be used to manufacture large-scale integrated circuits with lines below 0.1 μm, thereby eliminating the need to manufacture such highly integrated circuits in bulk silicon. Various parasitic effects produced by the device; (2) can be used to manufacture high-speed and low-power semiconductor devices required by various pocket devices; (3) can be used to manufacture semiconductor devices that are resistant to nuclear radiation; (4) form MOS Partial isolation of devices improves t...

AI Technical Summary

Problems solved by technology

[0006] The three existing methods for forming SOI wafers all have certain defects: after the oxygen injection and annealing process in the oxygen injection isolation technology, the crystal lattice of the single crystal silicon wafer will be destroyed, which greatly reduces the insulation performance of the insulating layer. This in turn reduces the quality of the SOI material

[0007] In the "bonded SOI" technology, the silicon substrate with a thickness of about several hundred microns should be uniformly polished or etched to a few microns or even 1 micron or less, which is technically in terms of controllability and uniformity. It is very difficult, and the production cost is very high; in addition, in the process of bonding to form SOI, if there are contaminants in the bonding surface or unevenness due to the poor flatness of the bonding surface, there will be pores Occurs at the bonding interface, affecting the quality of SOI wafers

[0008] "Smart Cut" technology requires high process precision, making production difficult and costly

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