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Method for encapsulating chip

A chip packaging and wafer technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of short circuit, easy electroplating precipitation, open circuit of outer leads, etc., to improve the packaging yield and process. The process is simple and the effect of improving packaging efficiency

Active Publication Date: 2011-04-27
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The existing wafer-level chip packaging method has the following problems: when using the electroplating process to make the outer leads 12, the metal in the dicing line (such as in the V-shaped groove described in the above-mentioned patent) is also easy to be electroplated and precipitated, resulting in a gap between the connecting wires. short circuit
In addition, after dicing, the side of the discrete chip, that is, the side wall of the original V-shaped groove, is exposed to the external environment, and is easily damaged when the shell is packaged, causing the outer lead to be disconnected, thereby affecting the yield of the chip.

Method used

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no. 1 example

[0059] Figure 8 is a schematic flow chart of the first embodiment of the present invention, and Figure 9 to Figure 16 It is a schematic diagram of each step in the above process, combined below Figure 8 Each step is described in detail.

[0060] Execute step S201;

[0061] Such as Figure 9 As shown, a semi-package wafer 10 is provided, and the semi-package wafer includes: a semiconductor substrate 100 formed with a chip, a dicing line 200 for dividing the wafer into several independent chip units, and a wafer located on the semiconductor substrate 100 The protection mask 101 has an opening, and the metal pad 102 of the chip is exposed in the opening. The protection mask 101 may be an organic film such as polyimide, and the metal pad 102 may be a conventional interconnection metal such as copper or aluminum.

[0062] It should be pointed out that the above-mentioned semiconductor substrate 100 is not limited to simple silicon or silicon-on-insulator substrate, and shou...

no. 2 example

[0094] Figure 22 is a schematic flow chart of the second embodiment of the present invention, and Figure 23 as well as Figure 24 It is a schematic diagram of some steps in the above process, and the following is combined Figure 22 Each step is described in detail.

[0095] Execute step S301;

[0096] A semi-packaged wafer is provided, and the semi-packaged wafer includes: a semiconductor substrate formed with a chip, a dicing line for dividing the wafer into several independent chip units, a protective mask with an opening on the semiconductor substrate, The metal pad of the chip is exposed in the opening. This step is the same as the first embodiment, see Figure 9 as well as Figure 10 .

[0097] Execute step S302;

[0098] Such as Figure 23 As shown, a mask plate 60 is provided on the surface of the wafer 10. The mask plate can be metallic glass or a hard mask plate made of other materials, which is closely attached to the wafer 10, and an opening is formed on...

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Abstract

The invention provides a method for encapsulating a chip. The method for encapsulating the chip comprises the following steps of: providing a semi-encapsulated wafer which is provided with a cutting channel and a metal welding pad; forming a below-ball metal electrode on the metal welding pad by a selective forming process; forming a protective layer on the part, except for the below-ball metal electrode, of the wafer, wherein the cutting channel is covered by the protective layer; forming a welding ball on the below-ball metal electrode; and scribing the wafer along the cutting channel. By the method, metal in the cutting channel is not influenced in the process of manufacturing the below-ball metal electrode; the side faces of the discrete chip can be protected after the cutting process; the process flow is simple; the encapsulation efficiency is improved; and the ratio of the finished products is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer-level chip packaging method. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted the traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier) mode, and complies with the market's increasingly light microelectronic products. , small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip si...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/56H01L23/00
CPCH01L2224/13611H01L2924/01023H01L2924/01082H01L2924/01029H01L2224/0401H01L2224/1147H01L2224/0347H01L21/78H01L24/11H01L2924/014H01L2224/94H01L2924/01013H01L2924/01024H01L2224/05572H01L2924/0103H01L2224/05644H01L2924/01047H01L2924/01079H01L2224/03462H01L23/3178H01L21/02008H01L2924/01033H01L2924/01006H01L23/3114H01L2924/01074H01L21/561H01L2224/05655H01L24/03H01L24/05H01L24/94H01L2224/05022H01L2224/05124H01L2224/05147H01L2224/11849H01L2224/131H01L2924/00013H01L2924/00014H01L2924/0002H01L2924/15788H01L2924/12042H01L2224/0384H01L2224/03831H01L2224/03H01L2224/11H01L2924/00012H01L2224/13099H01L2224/05099H01L2224/05599H01L2224/05552H01L2924/00
Inventor 石磊陶玉娟高国华舜田直实目黑弘一
Owner NANTONG FUJITSU MICROELECTRONICS